CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / tbm_patterns.ll

diff --git a/test/CodeGen/X86/tbm_patterns.ll b/test/CodeGen/X86/tbm_patterns.ll
index 8b999be0ea72eef69c427b51f15dfa80af4bed71..80d36d5af4d2cbb2fd4ea92656efb927208776e8 100644 (file)
--- a/test/CodeGen/X86/tbm_patterns.ll
+++ b/test/CodeGen/X86/tbm_patterns.ll
@@ -15,7 +15,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %0 = load i32* %a
+  %0 = load i32, i32* %a
   %1 = lshr i32 %0, 4
   %2 = and i32 %1, 4095
   ret i32 %2
@@ -36,7 +36,7 @@ entry:
   ; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
   ; CHECK-NOT: mov
   ; CHECK: bextr $
-  %0 = load i64* %a
+  %0 = load i64, i64* %a
   %1 = lshr i64 %0, 4
   %2 = and i64 %1, 4095
   ret i64 %2
@@ -84,6 +84,26 @@ entry:
   ret i64 %2
 }
 
+define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u32_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i32 -2, %a
+  %1 = or i32 %0, %a
+  ret i32 %1
+}
+
+define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u64_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i64 -2, %a
+  %1 = or i64 %0, %a
+  ret i64 %1
+}
+
 define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
 entry:
   ; CHECK-LABEL: test_x86_tbm_blcic_u32: