This commit enables unaligned memory accesses of vector types on AArch64 back end...

[oota-llvm.git] / test / CodeGen / X86 / twoaddr-coalesce.ll

diff --git a/test/CodeGen/X86/twoaddr-coalesce.ll b/test/CodeGen/X86/twoaddr-coalesce.ll
index c369d91f56aed8c85c50877f70b9609db8d24e79..6f6d6f2cd967167ba52330711e57509fff5b63bf 100644 (file)
--- a/test/CodeGen/X86/twoaddr-coalesce.ll
+++ b/test/CodeGen/X86/twoaddr-coalesce.ll
@@ -1,10 +1,9 @@
-; RUN: llvm-as < %s | llc -march=x86 -join-cross-class-copies -stats |& \
-; RUN:   grep {twoaddrinstr} | grep {Number of instructions aggressively commuted}
+; RUN: llc < %s -march=x86 | grep mov | count 4
 ; rdar://6523745
 
 @"\01LC" = internal constant [4 x i8] c"%d\0A\00"              ; <[4 x i8]*> [#uses=1]
 
-define i32 @main() nounwind {
+define i32 @foo() nounwind {
 bb1.thread:
        br label %bb1