CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / v8i1-masks.ll

diff --git a/test/CodeGen/X86/v8i1-masks.ll b/test/CodeGen/X86/v8i1-masks.ll
index 01079997a33f3751dd74b0875f8ba984281222f8..21fe963219876f5ae09d6efb54710486960aa2ba 100644 (file)
--- a/test/CodeGen/X86/v8i1-masks.ll
+++ b/test/CodeGen/X86/v8i1-masks.ll
@@ -1,38 +1,39 @@
 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
 
-;CHECK: and_masks
-;CHECK: vmovups
-;CHECK-NEXT: vcmpltp
-;CHECK-NEXT: vandps
-;CHECK-NEXT: vmovups
+;CHECK-LABEL: and_masks:
+;CHECK: vmovaps
+;CHECK: vcmpltp
+;CHECK: vcmpltp
+;CHECK: vandps
+;CHECK: vandps
+;CHECK: vmovaps
 ;CHECK: ret
 
 define void @and_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 16
-  %v1 = load <8 x float>* %b, align 16
+  %v0 = load <8 x float>, <8 x float>* %a, align 16
+  %v1 = load <8 x float>, <8 x float>* %b, align 16
   %m0 = fcmp olt <8 x float> %v1, %v0
-  %v2 = load <8 x float>* %c, align 16
+  %v2 = load <8 x float>, <8 x float>* %c, align 16
   %m1 = fcmp olt <8 x float> %v2, %v0
   %mand = and <8 x i1> %m1, %m0
   %r = zext <8 x i1> %mand to <8 x i32>
-  store <8 x i32> %r, <8 x i32>* undef, align 16
+  store <8 x i32> %r, <8 x i32>* undef, align 32
   ret void
 }
 
 ;CHECK: neg_mask
-;CHECK:  vmovups
-;CHECK-NEXT: vcmpltps
-;CHECK-NEXT: vandps
-;CHECK-NEXT: vmovups
+;CHECK: vcmpltps
+;CHECK: vxorps
+;CHECK: vandps
+;CHECK: vmovaps
 ;CHECK: ret
-
 define void @neg_masks(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
-  %v0 = load <8 x float>* %a, align 16
-  %v1 = load <8 x float>* %b, align 16
+  %v0 = load <8 x float>, <8 x float>* %a, align 16
+  %v1 = load <8 x float>, <8 x float>* %b, align 16
   %m0 = fcmp olt <8 x float> %v1, %v0
   %mand = xor <8 x i1> %m0, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
   %r = zext <8 x i1> %mand to <8 x i32>
-  store <8 x i32> %r, <8 x i32>* undef, align 16
+  store <8 x i32> %r, <8 x i32>* undef, align 32
   ret void
 }