CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / vec-sign.ll

diff --git a/test/CodeGen/X86/vec-sign.ll b/test/CodeGen/X86/vec-sign.ll
index 0d7e9e5e455d44a15ad28db565466067ac763c58..b3d85fd6ec7be75ac0e92b84a178302c0e68c73a 100644 (file)
--- a/test/CodeGen/X86/vec-sign.ll
+++ b/test/CodeGen/X86/vec-sign.ll
@@ -1,9 +1,11 @@
-; RUN: llc < %s -mcpu=nehalem | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=nehalem | FileCheck %s
 
-define <4 x i32> @psignd(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
+define <4 x i32> @signd(<4 x i32> %a, <4 x i32> %b) nounwind {
 entry:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
+; CHECK: ret
   %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
   %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -13,9 +15,11 @@ entry:
   ret <4 x i32> %cond
 }
 
-define <4 x i32> @pblendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind ssp {
+define <4 x i32> @blendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind {
 entry:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
+; CHECK: ret
   %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
   %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>