Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / vec_compare.ll

diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll
index 87d530dc1be78d7192ed9ca57f4dea5eef0aa38e..39c9b770d5f49903c742b0eaeef5d429766b3ef4 100644 (file)
--- a/test/CodeGen/X86/vec_compare.ll
+++ b/test/CodeGen/X86/vec_compare.ll
@@ -1,7 +1,43 @@
-; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep pcmpgtd
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
 
-define <4 x i32> @test(<4 x i32> %A, <4 x i32> %B) nounwind {
-       %C = vicmp sgt <4 x i32> %A, %B
-       ret <4 x i32> %C
+
+define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test1:
+; CHECK: pcmpgtd
+; CHECK: ret
+
+       %C = icmp sgt <4 x i32> %A, %B
+        %D = sext <4 x i1> %C to <4 x i32>
+       ret <4 x i32> %D
+}
+
+define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test2:
+; CHECK: pcmp
+; CHECK: pcmp
+; CHECK: pxor
+; CHECK: ret
+       %C = icmp sge <4 x i32> %A, %B
+        %D = sext <4 x i1> %C to <4 x i32>
+       ret <4 x i32> %D
 }
 
+define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test3:
+; CHECK: pcmpgtd
+; CHECK: movdqa
+; CHECK: ret
+       %C = icmp slt <4 x i32> %A, %B
+        %D = sext <4 x i1> %C to <4 x i32>
+       ret <4 x i32> %D
+}
+
+define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test4:
+; CHECK: movdqa
+; CHECK: pcmpgtd
+; CHECK: ret
+       %C = icmp ugt <4 x i32> %A, %B
+        %D = sext <4 x i1> %C to <4 x i32>
+       ret <4 x i32> %D
+}