Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / vec_fneg.ll

diff --git a/test/CodeGen/X86/vec_fneg.ll b/test/CodeGen/X86/vec_fneg.ll
index 0a057a4fd02727a2489dd1499401ce25755124c2..d49c70e563911e510486006aab498a21871e6d92 100644 (file)
--- a/test/CodeGen/X86/vec_fneg.ll
+++ b/test/CodeGen/X86/vec_fneg.ll
@@ -1,11 +1,11 @@
-; RUN: llvm-as < %s | | llc -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2
 
 define <4 x float> @t1(<4 x float> %Q) {
-        %tmp15 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
+        %tmp15 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
        ret <4 x float> %tmp15
 }
 
 define <4 x float> @t2(<4 x float> %Q) {
-        %tmp15 = sub <4 x float> zeroinitializer, %Q
+        %tmp15 = fsub <4 x float> zeroinitializer, %Q
        ret <4 x float> %tmp15
 }