Let the inline asm 'q' constraint match float, and on 64-bit double too.

[oota-llvm.git] / test / CodeGen / X86 / vec_set-9.ll

diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll
index b73187c055d2efa5190bb0b0f61713131bb29bea..3656e5f6ca47b1972ef2ab4ea672faf18bdb1100 100644 (file)
--- a/test/CodeGen/X86/vec_set-9.ll
+++ b/test/CodeGen/X86/vec_set-9.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1
-; RUN: llvm-as < %s | llc -march=x86-64 | grep {punpcklqdq.*%xmm0, %xmm0}
+; RUN: llc < %s -march=x86-64 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
 
-define <2 x i64> @test3(i64 %A) {
+define <2 x i64> @test3(i64 %A) nounwind {
 entry:
        %B = insertelement <2 x i64> undef, i64 %A, i32 1
        ret <2 x i64> %B