Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / vec_shuffle-22.ll

diff --git a/test/CodeGen/X86/vec_shuffle-22.ll b/test/CodeGen/X86/vec_shuffle-22.ll
index 5648356333bf354c205ba3c96588db48eb54b09b..6807e4d639092a40dfb8b41386fb5e1b0fe90612 100644 (file)
--- a/test/CodeGen/X86/vec_shuffle-22.ll
+++ b/test/CodeGen/X86/vec_shuffle-22.ll
@@ -1,16 +1,15 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2       | not grep shuf
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse3 | grep movlhps | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse3       | grep movddup | count 1
+; RUN: llc < %s -march=x86 -mcpu=pentium-m  | FileCheck %s
 
 define <4 x float> @t1(<4 x float> %a) nounwind  {
-entry:
-        %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 >       ; <<4 x float>> [#uses=1]
-        ret <4 x float> %tmp1
+; CHECK: movlhps
+  %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 >       ; <<4 x float>> [#uses=1]
+  ret <4 x float> %tmp1
 }
 
 define <4 x i32> @t2(<4 x i32>* %a) nounwind {
-entry:
-        %tmp1 = load <4 x i32>* %a;
+; CHECK: pshufd
+; CHECK: ret
+  %tmp1 = load <4 x i32>* %a
        %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 >                ; <<4 x i32>> [#uses=1]
        ret <4 x i32> %tmp2
 }