Implement a feature (-vector-unaligned-mem) to allow targets to

[oota-llvm.git] / test / CodeGen / X86 / vec_shuffle-8.ll

diff --git a/test/CodeGen/X86/vec_shuffle-8.ll b/test/CodeGen/X86/vec_shuffle-8.ll
index 13e8b9c22a236451d899ba1a74b6dcc64c79670b..964ce7b2892be7a6c76b4354b210fdc486221e6d 100644 (file)
--- a/test/CodeGen/X86/vec_shuffle-8.ll
+++ b/test/CodeGen/X86/vec_shuffle-8.ll
@@ -1,9 +1,10 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -mattr=+sse2 &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -mattr=+sse2 | not grep shufps
+; RUN: llc < %s -march=x86 -mattr=+sse2 | \
+; RUN:   not grep shufps
 
-void %test(<4 x float>* %res, <4 x float>* %A) {
-       %tmp1 = load <4 x float>* %A
-       %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x uint> < uint 0, uint 5, uint 6, uint 7 >
-       store <4 x float> %tmp2, <4 x float>* %res
-       ret void
+define void @test(<4 x float>* %res, <4 x float>* %A) {
+        %tmp1 = load <4 x float>* %A            ; <<4 x float>> [#uses=1]
+        %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >          ; <<4 x float>> [#uses=1]
+        store <4 x float> %tmp2, <4 x float>* %res
+        ret void
 }
+