CodeGen peephole: fold redundant phys reg copies

[oota-llvm.git] / test / CodeGen / X86 / vselect-2.ll

diff --git a/test/CodeGen/X86/vselect-2.ll b/test/CodeGen/X86/vselect-2.ll
index 0991bdacd9c50aa84dd2cd7a05054a16bf559703..8e0f4a4ef4475f874aae857411625a6553132d13 100644 (file)
--- a/test/CodeGen/X86/vselect-2.ll
+++ b/test/CodeGen/X86/vselect-2.ll
@@ -1,14 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
-; SSE2-LABEL: test1
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm0, %xmm1
-; SSE2-NEXT:     movaps %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test1:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test1
+; SSE41-LABEL: test1:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
 ; SSE41-NEXT:    retq
@@ -17,12 +18,12 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
-; SSE2-LABEL: test2
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test2:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test2
+; SSE41-LABEL: test2:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
 ; SSE41-NEXT:    retq
@@ -31,13 +32,13 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
 }
 
 define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
-; SSE2-LABEL: test3
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm0, %xmm1
-; SSE2-NEXT:     movaps %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test3:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
+; SSE2-NEXT:    movapd %xmm1, %xmm0
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test3
+; SSE41-LABEL: test3:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
 ; SSE41-NEXT:    retq
@@ -46,12 +47,12 @@ define <4 x float> @test3(<4 x float> %A, <4 x float> %B) {
 }
 
 define <4 x float> @test4(<4 x float> %A, <4 x float> %B) {
-; SSE2-LABEL: test4
-; SSE2:        # BB#0:
-; SSE2-NEXT:     movsd %xmm1, %xmm0
-; SSE2-NEXT:     retq
+; SSE2-LABEL: test4:
+; SSE2:       # BB#0:
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
+; SSE2-NEXT:    retq
 ;
-; SSE41-LABEL: test4
+; SSE41-LABEL: test4:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE41-NEXT:    retq