Enable all Hexagon tests.

[oota-llvm.git] / test / CodeGen / X86 / xor.ll

diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 9bfff8a06a862c382d8a8411e792380cf049c6ee..ddc4cab14a4c55d52c221e14d77fc58ac8815f49 100644 (file)
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2  | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
 
 ; Though it is undefined, we want xor undef,undef to produce zero.
 define <4 x i32> @test1() nounwind {
@@ -28,9 +29,8 @@ entry:
         ret i32 %tmp4
         
 ; X64: test3:
-; X64: notl    %esi
-; X64: andl    %edi, %esi
-; X64: movl    %esi, %eax
+; X64: notl
+; X64: andl
 ; X64: shrl    %eax
 ; X64: ret
 
@@ -80,11 +80,11 @@ bb:
 bb12:
        ret i16 %tmp3
 ; X64: test5:
-; X64:    notw [[REG:%[a-z]+]]
-; X64:    andw {{.*}}[[REG]]
+; X64:    notl [[REG:%[a-z]+]]
+; X64:    andl {{.*}}[[REG]]
 ; X32: test5:
-; X32:    notw [[REG:%[a-z]+]]
-; X32:    andw {{.*}}[[REG]]
+; X32:    notl [[REG:%[a-z]+]]
+; X32:    andl {{.*}}[[REG]]
 }
 
 define i8 @test6(i8 %a, i8 %b) nounwind  {
@@ -138,7 +138,7 @@ entry:
   %t2 = add i32 %t1, -1
   ret i32 %t2
 ; X64: test8:
-; X64:   notl %eax
+; X64:   notl {{%eax|%edi|%ecx}}
 ; X32: test8:
 ; X32:   notl %eax
 }