[x32] Fix FrameIndex check in SelectLEA64_32Addr

[oota-llvm.git] / test / CodeGen / X86 / xor.ll

diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 86ecbe5ec7eb99516bb9818954afd15587154360..fd8e1b4cebaa4043a21a345a66a55964df0cd095 100644 (file)
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -1,12 +1,13 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2  | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2  | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
 
 ; Though it is undefined, we want xor undef,undef to produce zero.
 define <4 x i32> @test1() nounwind {
        %tmp = xor <4 x i32> undef, undef
        ret <4 x i32> %tmp
         
-; X32: test1:
+; X32-LABEL: test1:
 ; X32: xorps   %xmm0, %xmm0
 ; X32: ret
 }
@@ -15,7 +16,7 @@ define <4 x i32> @test1() nounwind {
 define i32 @test2() nounwind{
        %tmp = xor i32 undef, undef
        ret i32 %tmp
-; X32: test2:
+; X32-LABEL: test2:
 ; X32: xorl    %eax, %eax
 ; X32: ret
 }
@@ -27,14 +28,13 @@ entry:
         %tmp4 = lshr i32 %tmp3, 1
         ret i32 %tmp4
         
-; X64: test3:
-; X64: notl    %esi
-; X64: andl    %edi, %esi
-; X64: movl    %esi, %eax
-; X64: shrl    %eax
+; X64-LABEL: test3:
+; X64: notl
+; X64: andl
+; X64: shrl
 ; X64: ret
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32:         movl    8(%esp), %eax
 ; X32:         notl    %eax
 ; X32:         andl    4(%esp), %eax
@@ -57,12 +57,12 @@ bb:
 bb12:
        ret i32 %tmp3
         
-; X64: test4:
-; X64:    notl %eax
-; X64:    andl {{.*%eax}}
-; X32: test4:
-; X32:    notl %edx
-; X32:    andl {{.*%edx}}
+; X64-LABEL: test4:
+; X64:    notl [[REG:%[a-z]+]]
+; X64:    andl {{.*}}[[REG]]
+; X32-LABEL: test4:
+; X32:    notl [[REG:%[a-z]+]]
+; X32:    andl {{.*}}[[REG]]
 }
 
 define i16 @test5(i16 %a, i16 %b) nounwind  {
@@ -79,12 +79,12 @@ bb:
        br i1 %tmp10, label %bb12, label %bb
 bb12:
        ret i16 %tmp3
-; X64: test5:
-; X64:    notw %ax
-; X64:    andw {{.*%ax}}
-; X32: test5:
-; X32:    notw %dx
-; X32:    andw {{.*%dx}}
+; X64-LABEL: test5:
+; X64:    notl [[REG:%[a-z]+]]
+; X64:    andl {{.*}}[[REG]]
+; X32-LABEL: test5:
+; X32:    notl [[REG:%[a-z]+]]
+; X32:    andl {{.*}}[[REG]]
 }
 
 define i8 @test6(i8 %a, i8 %b) nounwind  {
@@ -101,12 +101,12 @@ bb:
        br i1 %tmp10, label %bb12, label %bb
 bb12:
        ret i8 %tmp3
-; X64: test6:
-; X64:    notb %al
-; X64:    andb {{.*%al}}
-; X32: test6:
-; X32:    notb %dl
-; X32:    andb {{.*%dl}}
+; X64-LABEL: test6:
+; X64:    notb [[REG:%[a-z]+]]
+; X64:    andb {{.*}}[[REG]]
+; X32-LABEL: test6:
+; X32:    notb [[REG:%[a-z]+]]
+; X32:    andb {{.*}}[[REG]]
 }
 
 define i32 @test7(i32 %a, i32 %b) nounwind  {
@@ -123,11 +123,61 @@ bb:
        br i1 %tmp10, label %bb12, label %bb
 bb12:
        ret i32 %tmp3
-; X64: test7:
-; X64:    xorl $2147483646, %eax
-; X64:    andl {{.*%eax}}
-; X32: test7:
-; X32:    xorl $2147483646, %edx
-; X32:    andl {{.*%edx}}
+; X64-LABEL: test7:
+; X64:    xorl $2147483646, [[REG:%[a-z]+]]
+; X64:    andl {{.*}}[[REG]]
+; X32-LABEL: test7:
+; X32:    xorl $2147483646, [[REG:%[a-z]+]]
+; X32:    andl {{.*}}[[REG]]
 }
 
+define i32 @test8(i32 %a) nounwind {
+; rdar://7553032
+entry:
+  %t1 = sub i32 0, %a
+  %t2 = add i32 %t1, -1
+  ret i32 %t2
+; X64-LABEL: test8:
+; X64:   notl {{%eax|%edi|%ecx}}
+; X32-LABEL: test8:
+; X32:   notl %eax
+}
+
+define i32 @test9(i32 %a) nounwind {
+  %1 = and i32 %a, 4096
+  %2 = xor i32 %1, 4096
+  ret i32 %2
+; X64-LABEL: test9:
+; X64:    notl [[REG:%[a-z]+]]
+; X64:    andl {{.*}}[[REG:%[a-z]+]]
+; X32-LABEL: test9:
+; X32:    notl [[REG:%[a-z]+]]
+; X32:    andl {{.*}}[[REG:%[a-z]+]]
+}
+
+; PR15948
+define <4 x i32> @test10(<4 x i32> %a) nounwind {
+  %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
+  %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
+  ret <4 x i32> %2
+; X64-LABEL: test10:
+; X64:    andnps
+; X32-LABEL: test10:
+; X32:    andnps
+}
+
+define i32 @PR17487(i1 %tobool) {
+  %tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1
+  %tmp1 = zext <2 x i1> %tmp to <2 x i64>
+  %tmp2 = xor <2 x i64> %tmp1, <i64 1, i64 1>
+  %tmp3 = extractelement <2 x i64> %tmp2, i32 1
+  %add = add nsw i64 0, %tmp3
+  %cmp6 = icmp ne i64 %add, 1
+  %conv7 = zext i1 %cmp6 to i32
+  ret i32 %conv7
+
+; X64-LABEL: PR17487:
+; X64: andn
+; X32-LABEL: PR17487:
+; X32: andn
+}