Support for Hexagon VLIW Packetizer.

[oota-llvm.git] / test / CodeGen / XCore / ashr.ll

diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
index d585e8b10d98feb438f6fde3b69326fe2f685bb9..03b6b1f1695039ebe3f2b5647219a48e1508c057 100644 (file)
--- a/test/CodeGen/XCore/ashr.ll
+++ b/test/CodeGen/XCore/ashr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
 define i32 @ashr(i32 %a, i32 %b) {
        %1 = ashr i32 %a, %b
        ret i32 %1
@@ -30,7 +30,7 @@ not_less:
 }
 ; CHECK: f1:
 ; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
+; CHECK-NEXT: bt r0
 
 define i32 @f2(i32 %a) {
         %1 = icmp sge i32 %a, 0
@@ -50,10 +50,10 @@ define i32 @f3(i32 %a) {
        ret i32 %2
 }
 ; CHECK: f3:
-; CHECK-NEXT: ashr r1, r0, 32
-; CHECK-NEXT: ldc r0, 10
-; CHECK-NEXT: bt r1
-; CHECK: ldc r0, 17
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 17
+; CHECK: ldc r0, 10
 
 define i32 @f4(i32 %a) {
         %1 = icmp sge i32 %a, 0
@@ -61,10 +61,10 @@ define i32 @f4(i32 %a) {
        ret i32 %2
 }
 ; CHECK: f4:
-; CHECK-NEXT: ashr r1, r0, 32
-; CHECK-NEXT: ldc r0, 17
-; CHECK-NEXT: bt r1
-; CHECK: ldc r0, 10
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 10
+; CHECK: ldc r0, 17
 
 define i32 @f5(i32 %a) {
         %1 = icmp sge i32 %a, 0