Support for Hexagon VLIW Packetizer.

[oota-llvm.git] / test / CodeGen / XCore / mul64.ll

diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
index c06fe5a20b3aec889c35aaea0836388060cf3cd1..3d373b194153f9cfb9fddaa12a33329d910f4ad7 100644 (file)
--- a/test/CodeGen/XCore/mul64.ll
+++ b/test/CodeGen/XCore/mul64.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
 define i64 @umul_lohi(i32 %a, i32 %b) {
 entry:
        %0 = zext i32 %a to i64
@@ -7,8 +8,8 @@ entry:
        ret i64 %2
 }
 ; CHECK: umul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
+; CHECK: ldc [[REG:r[0-9]+]], 0
+; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
 ; CHECK-NEXT: retsp 0
 
 define i64 @smul_lohi(i32 %a, i32 %b) {
@@ -19,9 +20,31 @@ entry:
        ret i64 %2
 }
 ; CHECK: smul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: maccs r2, r3, r1, r0
-; CHECK-NEXT: mov r0, r3
-; CHECK-NEXT: mov r1, r2
-; CHECK-NEXT: retsp 0
+; CHECK: ldc
+; CHECK-NEXT: mov
+; CHECK-NEXT: maccs
+; CHECK: retsp 0
+
+define i64 @mul64(i64 %a, i64 %b) {
+entry:
+       %0 = mul i64 %a, %b
+       ret i64 %0
+}
+; CHECK: mul64:
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: lmul
+
+define i64 @mul64_2(i64 %a, i32 %b) {
+entry:
+       %0 = zext i32 %b to i64
+       %1 = mul i64 %a, %0
+       ret i64 %1
+}
+; CHECK: mul64_2:
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: add r1,
+; CHECK: retsp 0