Hexagon: Add support to generate predicated absolute addressing mode

[oota-llvm.git] / test / ExecutionEngine / 2003-01-09-SARTest.ll

diff --git a/test/ExecutionEngine/2003-01-09-SARTest.ll b/test/ExecutionEngine/2003-01-09-SARTest.ll
index b19a93172fec285a9233bb9b5dd48d0f68e34152..ed58e118437769e014f56fb18189c26171336ee7 100644 (file)
--- a/test/ExecutionEngine/2003-01-09-SARTest.ll
+++ b/test/ExecutionEngine/2003-01-09-SARTest.ll
@@ -1,8 +1,11 @@
+; RUN: %lli %s > /dev/null
+
 ; We were accidentally inverting the signedness of right shifts.  Whoops.
 
-int %main() {
-  %X = shr int -1, ubyte 16
-  %Y = shr int %X, ubyte 16
-  %Z = add int %Y, 1
-  ret int %Z
+define i32 @main() {
+       %X = ashr i32 -1, 16            ; <i32> [#uses=1]
+       %Y = ashr i32 %X, 16            ; <i32> [#uses=1]
+       %Z = add i32 %Y, 1              ; <i32> [#uses=1]
+       ret i32 %Z
 }
+