The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions

[oota-llvm.git] / test / Integer / testlogical_new_bt.ll

diff --git a/test/Integer/testlogical_new_bt.ll b/test/Integer/testlogical_new_bt.ll
index 72675dea1d25cc0ffd4fbdc49e496572b176470b..49a26dc07b070945881214cac16708c680e9b22b 100644 (file)
--- a/test/Integer/testlogical_new_bt.ll
+++ b/test/Integer/testlogical_new_bt.ll
@@ -2,15 +2,14 @@
 ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
 ; RUN: diff %t1.ll %t2.ll
 
-implementation
 
-define i31 "simpleAdd"(i31 %i0, i31 %j0)
+define i31 @"simpleAdd"(i31 %i0, i31 %j0)
 begin
        %t1 = xor i31 %i0, %j0
        %t2 = or i31 %i0, %j0
        %t3 = and i31 %t1, %t2
-        %t4 = shl i31 %i0, i8 2
-        %t5 = ashr i31 %i0, i8 2
-        %t6 = lshr i31 %j0, i8 22
+        %t4 = shl i31 %i0, 2
+        %t5 = ashr i31 %i0, 2
+        %t6 = lshr i31 %j0, 22
        ret i31 %t3
 end