@------------------------------------------------------------------------------
@ ADC (immediate)
@------------------------------------------------------------------------------
- adc r1, r2, #0xf
- adc r1, r2, #0xf0
- adc r1, r2, #0xf00
- adc r1, r2, #0xf000
- adc r1, r2, #0xf0000
- adc r1, r2, #0xf00000
- adc r1, r2, #0xf000000
- adc r1, r2, #0xf0000000
- adc r1, r2, #0xf000000f
- adcs r1, r2, #0xf00
- adcseq r1, r2, #0xf00
- adceq r1, r2, #0xf00
+ adc r1, r2, #0xf
+ adc r1, r2, #0xf0
+ adc r1, r2, #0xf00
+ adc r1, r2, #0xf000
+ adc r1, r2, #0xf0000
+ adc r1, r2, #0xf00000
+ adc r1, r2, #0xf000000
+ adc r1, r2, #0xf0000000
+ adc r1, r2, #0xf000000f
+ adcs r1, r2, #0xf00
+ adcseq r1, r2, #0xf00
+ adceq r1, r2, #0xf00
@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
@ ADC (register)
@ ADC (shifted register)
@------------------------------------------------------------------------------
- adc r4, r5, r6
- @ Constant shifts
- adc r4, r5, r6, lsl #1
- adc r4, r5, r6, lsl #31
- adc r4, r5, r6, lsr #1
- adc r4, r5, r6, lsr #31
- adc r4, r5, r6, lsr #32
- adc r4, r5, r6, asr #1
- adc r4, r5, r6, asr #31
- adc r4, r5, r6, asr #32
- adc r4, r5, r6, ror #1
- adc r4, r5, r6, ror #31
-
- @ Register shifts
- adc r6, r7, r8, lsl r9
- adc r6, r7, r8, lsr r9
- adc r6, r7, r8, asr r9
- adc r6, r7, r8, ror r9
- adc r4, r5, r6, rrx
-
- @ Destination register is optional
- adc r5, r6
- adc r4, r5, lsl #1
- adc r4, r5, lsl #31
- adc r4, r5, lsr #1
- adc r4, r5, lsr #31
- adc r4, r5, lsr #32
- adc r4, r5, asr #1
- adc r4, r5, asr #31
- adc r4, r5, asr #32
- adc r4, r5, ror #1
- adc r4, r5, ror #31
- adc r4, r5, rrx
- adc r6, r7, lsl r9
- adc r6, r7, lsr r9
- adc r6, r7, asr r9
- adc r6, r7, ror r9
- adc r4, r5, rrx
+ adc r4, r5, r6
+ @ Constant shifts
+ adc r4, r5, r6, lsl #1
+ adc r4, r5, r6, lsl #31
+ adc r4, r5, r6, lsr #1
+ adc r4, r5, r6, lsr #31
+ adc r4, r5, r6, lsr #32
+ adc r4, r5, r6, asr #1
+ adc r4, r5, r6, asr #31
+ adc r4, r5, r6, asr #32
+ adc r4, r5, r6, ror #1
+ adc r4, r5, r6, ror #31
+
+ @ Register shifts
+ adc r6, r7, r8, lsl r9
+ adc r6, r7, r8, lsr r9
+ adc r6, r7, r8, asr r9
+ adc r6, r7, r8, ror r9
+ adc r4, r5, r6, rrx
+
+ @ Destination register is optional
+ adc r5, r6
+ adc r4, r5, lsl #1
+ adc r4, r5, lsl #31
+ adc r4, r5, lsr #1
+ adc r4, r5, lsr #31
+ adc r4, r5, lsr #32
+ adc r4, r5, asr #1
+ adc r4, r5, asr #31
+ adc r4, r5, asr #32
+ adc r4, r5, ror #1
+ adc r4, r5, ror #31
+ adc r4, r5, rrx
+ adc r6, r7, lsl r9
+ adc r6, r7, lsr r9
+ adc r6, r7, asr r9
+ adc r6, r7, ror r9
+ adc r4, r5, rrx
@ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0]
@ ADR
@------------------------------------------------------------------------------
Lback:
- adr r2, Lback
- adr r3, Lforward
+ adr r2, Lback
+ adr r3, Lforward
Lforward:
+ adr r2, #3
+ adr r2, #-3
@ CHECK: Lback:
@ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A]
@ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A]
@ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12
@ CHECK: Lforward:
+@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2]
+@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2]
@------------------------------------------------------------------------------
@ ADD
@------------------------------------------------------------------------------
- add r4, r5, #0xf000
- add r4, r5, r6
- add r4, r5, r6, lsl #5
- add r4, r5, r6, lsr #5
- add r4, r5, r6, lsr #5
- add r4, r5, r6, asr #5
- add r4, r5, r6, ror #5
- add r6, r7, r8, lsl r9
- add r6, r7, r8, lsr r9
- add r6, r7, r8, asr r9
- add r6, r7, r8, ror r9
- add r4, r5, r6, rrx
-
- @ destination register is optional
- add r5, #0xf000
- add r4, r5
- add r4, r5, lsl #5
- add r4, r5, lsr #5
- add r4, r5, lsr #5
- add r4, r5, asr #5
- add r4, r5, ror #5
- add r6, r7, lsl r9
- add r6, r7, lsr r9
- add r6, r7, asr r9
- add r6, r7, ror r9
- add r4, r5, rrx
+ add r4, r5, #0xf000
+ add r4, r5, r6
+ add r4, r5, r6, lsl #5
+ add r4, r5, r6, lsr #5
+ add r4, r5, r6, lsr #5
+ add r4, r5, r6, asr #5
+ add r4, r5, r6, ror #5
+ add r6, r7, r8, lsl r9
+ add r6, r7, r8, lsr r9
+ add r6, r7, r8, asr r9
+ add r6, r7, r8, ror r9
+ add r4, r5, r6, rrx
+
+ @ destination register is optional
+ add r5, #0xf000
+ add r4, r5
+ add r4, r5, lsl #5
+ add r4, r5, lsr #5
+ add r4, r5, lsr #5
+ add r4, r5, asr #5
+ add r4, r5, ror #5
+ add r6, r7, lsl r9
+ add r6, r7, lsr r9
+ add r6, r7, asr r9
+ add r6, r7, ror r9
+ add r4, r5, rrx
@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
@------------------------------------------------------------------------------
@ AND
@------------------------------------------------------------------------------
- and r10, r1, #0xf
- and r10, r1, r6
- and r10, r1, r6, lsl #10
- and r10, r1, r6, lsr #10
- and r10, r1, r6, lsr #10
- and r10, r1, r6, asr #10
- and r10, r1, r6, ror #10
- and r6, r7, r8, lsl r2
- and r6, r7, r8, lsr r2
- and r6, r7, r8, asr r2
- and r6, r7, r8, ror r2
- and r10, r1, r6, rrx
-
- @ destination register is optional
- and r1, #0xf
- and r10, r1
- and r10, r1, lsl #10
- and r10, r1, lsr #10
- and r10, r1, lsr #10
- and r10, r1, asr #10
- and r10, r1, ror #10
- and r6, r7, lsl r2
- and r6, r7, lsr r2
- and r6, r7, asr r2
- and r6, r7, ror r2
- and r10, r1, rrx
+ and r10, r1, #0xf
+ and r10, r1, r6
+ and r10, r1, r6, lsl #10
+ and r10, r1, r6, lsr #10
+ and r10, r1, r6, lsr #10
+ and r10, r1, r6, asr #10
+ and r10, r1, r6, ror #10
+ and r6, r7, r8, lsl r2
+ and r6, r7, r8, lsr r2
+ and r6, r7, r8, asr r2
+ and r6, r7, r8, ror r2
+ and r10, r1, r6, rrx
+
+ @ destination register is optional
+ and r1, #0xf
+ and r10, r1
+ and r10, r1, lsl #10
+ and r10, r1, lsr #10
+ and r10, r1, lsr #10
+ and r10, r1, asr #10
+ and r10, r1, ror #10
+ and r6, r7, lsl r2
+ and r6, r7, lsr r2
+ and r6, r7, asr r2
+ and r6, r7, ror r2
+ and r10, r1, rrx
@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
beq _baz
@ CHECK: b _bar @ encoding: [A,A,A,0xea]
- @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
+ @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
@ CHECK: beq _baz @ encoding: [A,A,A,0x0a]
- @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
+ @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch
@------------------------------------------------------------------------------
@ BFC
@------------------------------------------------------------------------------
- bfc r5, #3, #17
- bfccc r5, #3, #17
+ bfc r5, #3, #17
+ bfccc r5, #3, #17
@ CHECK: bfc r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0xe7]
@ CHECK: bfclo r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0x37]
@------------------------------------------------------------------------------
@ BFI
@------------------------------------------------------------------------------
- bfi r5, r2, #3, #17
- bfine r5, r2, #3, #17
+ bfi r5, r2, #3, #17
+ bfine r5, r2, #3, #17
@ CHECK: bfi r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0xe7]
@ CHECK: bfine r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0x17]
@------------------------------------------------------------------------------
@ BIC
@------------------------------------------------------------------------------
- bic r10, r1, #0xf
- bic r10, r1, r6
- bic r10, r1, r6, lsl #10
- bic r10, r1, r6, lsr #10
- bic r10, r1, r6, lsr #10
- bic r10, r1, r6, asr #10
- bic r10, r1, r6, ror #10
- bic r6, r7, r8, lsl r2
- bic r6, r7, r8, lsr r2
- bic r6, r7, r8, asr r2
- bic r6, r7, r8, ror r2
- bic r10, r1, r6, rrx
-
- @ destination register is optional
- bic r1, #0xf
- bic r10, r1
- bic r10, r1, lsl #10
- bic r10, r1, lsr #10
- bic r10, r1, lsr #10
- bic r10, r1, asr #10
- bic r10, r1, ror #10
- bic r6, r7, lsl r2
- bic r6, r7, lsr r2
- bic r6, r7, asr r2
- bic r6, r7, ror r2
- bic r10, r1, rrx
+ bic r10, r1, #0xf
+ bic r10, r1, r6
+ bic r10, r1, r6, lsl #10
+ bic r10, r1, r6, lsr #10
+ bic r10, r1, r6, lsr #10
+ bic r10, r1, r6, asr #10
+ bic r10, r1, r6, ror #10
+ bic r6, r7, r8, lsl r2
+ bic r6, r7, r8, lsr r2
+ bic r6, r7, r8, asr r2
+ bic r6, r7, r8, ror r2
+ bic r10, r1, r6, rrx
+
+ @ destination register is optional
+ bic r1, #0xf
+ bic r10, r1
+ bic r10, r1, lsl #10
+ bic r10, r1, lsr #10
+ bic r10, r1, lsr #10
+ bic r10, r1, asr #10
+ bic r10, r1, ror #10
+ bic r6, r7, lsl r2
+ bic r6, r7, lsr r2
+ bic r6, r7, asr r2
+ bic r6, r7, ror r2
+ bic r10, r1, rrx
@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
@------------------------------------------------------------------------------
@ BKPT
@------------------------------------------------------------------------------
- bkpt #10
- bkpt #65535
+ bkpt #10
+ bkpt #65535
@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
@ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1]
@ BL/BLX (immediate)
@------------------------------------------------------------------------------
- bl _bar
- blx _bar
+ bl _bar
+ blx _bar
+ blls #28634268
+ blx #32424576
+ blx #16212288
@ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
@ CHECK: blx _bar @ encoding: [A,A,A,0xfa]
@ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
-
+@ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b]
+@ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa]
+@ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa]
@------------------------------------------------------------------------------
@ BLX (register)
@------------------------------------------------------------------------------
- blx r2
- blxne r2
+ blx r2
+ blxne r2
@ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1]
@ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11]
@------------------------------------------------------------------------------
@ BX
@------------------------------------------------------------------------------
-
- bx r2
- bxne r2
+ bx r2
+ bxne r2
@ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1]
@ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11]
@------------------------------------------------------------------------------
@ BXJ
@------------------------------------------------------------------------------
-
- bxj r2
- bxjne r2
+ bxj r2
+ bxjne r2
@ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1]
@ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11]
@------------------------------------------------------------------------------
@ CDP/CDP2
@------------------------------------------------------------------------------
- cdp p7, #1, c1, c1, c1, #4
- cdp2 p7, #1, c1, c1, c1, #4
+ cdp p7, #1, c1, c1, c1, #4
+ cdp2 p7, #1, c1, c1, c1, #4
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
@------------------------------------------------------------------------------
@ CLREX
@------------------------------------------------------------------------------
- clrex
+ clrex
@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5]
@------------------------------------------------------------------------------
@ CLZ
@------------------------------------------------------------------------------
- clz r1, r2
- clzeq r1, r2
+ clz r1, r2
+ clzeq r1, r2
@ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1]
@ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01]
@------------------------------------------------------------------------------
@ CMN
@------------------------------------------------------------------------------
- cmn r1, #0xf
- cmn r1, r6
- cmn r1, r6, lsl #10
- cmn r1, r6, lsr #10
- cmn sp, r6, lsr #10
- cmn r1, r6, asr #10
- cmn r1, r6, ror #10
- cmn r7, r8, lsl r2
- cmn sp, r8, lsr r2
- cmn r7, r8, asr r2
- cmn r7, r8, ror r2
- cmn r1, r6, rrx
+ cmn r1, #0xf
+ cmn r1, r6
+ cmn r1, r6, lsl #10
+ cmn r1, r6, lsr #10
+ cmn sp, r6, lsr #10
+ cmn r1, r6, asr #10
+ cmn r1, r6, ror #10
+ cmn r7, r8, lsl r2
+ cmn sp, r8, lsr r2
+ cmn r7, r8, asr r2
+ cmn r7, r8, ror r2
+ cmn r1, r6, rrx
@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
@------------------------------------------------------------------------------
@ CMP
@------------------------------------------------------------------------------
- cmp r1, #0xf
- cmp r1, r6
- cmp r1, r6, lsl #10
- cmp r1, r6, lsr #10
- cmp sp, r6, lsr #10
- cmp r1, r6, asr #10
- cmp r1, r6, ror #10
- cmp r7, r8, lsl r2
- cmp sp, r8, lsr r2
- cmp r7, r8, asr r2
- cmp r7, r8, ror r2
- cmp r1, r6, rrx
+ cmp r1, #0xf
+ cmp r1, r6
+ cmp r1, r6, lsl #10
+ cmp r1, r6, lsr #10
+ cmp sp, r6, lsr #10
+ cmp r1, r6, asr #10
+ cmp r1, r6, ror #10
+ cmp r7, r8, lsl r2
+ cmp sp, r8, lsr r2
+ cmp r7, r8, asr r2
+ cmp r7, r8, ror r2
+ cmp r1, r6, rrx
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
@------------------------------------------------------------------------------
@ DBG
@------------------------------------------------------------------------------
- dbg #0
- dbg #5
- dbg #15
+ dbg #0
+ dbg #5
+ dbg #15
@ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3]
@ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3]
@------------------------------------------------------------------------------
@ DMB
@------------------------------------------------------------------------------
- dmb sy
- dmb st
- dmb sh
- dmb ish
- dmb shst
- dmb ishst
- dmb un
- dmb nsh
- dmb unst
- dmb nshst
- dmb osh
- dmb oshst
- dmb
+ dmb sy
+ dmb st
+ dmb sh
+ dmb ish
+ dmb shst
+ dmb ishst
+ dmb un
+ dmb nsh
+ dmb unst
+ dmb nshst
+ dmb osh
+ dmb oshst
+ dmb
@ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5]
@ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5]
@------------------------------------------------------------------------------
@ DSB
@------------------------------------------------------------------------------
- dsb sy
- dsb st
- dsb sh
- dsb ish
- dsb shst
- dsb ishst
- dsb un
- dsb nsh
- dsb unst
- dsb nshst
- dsb osh
- dsb oshst
- dsb
+ dsb sy
+ dsb st
+ dsb sh
+ dsb ish
+ dsb shst
+ dsb ishst
+ dsb un
+ dsb nsh
+ dsb unst
+ dsb nshst
+ dsb osh
+ dsb oshst
+ dsb
@ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5]
@ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5]
@------------------------------------------------------------------------------
@ EOR
@------------------------------------------------------------------------------
- eor r4, r5, #0xf000
- eor r4, r5, r6
- eor r4, r5, r6, lsl #5
- eor r4, r5, r6, lsr #5
- eor r4, r5, r6, lsr #5
- eor r4, r5, r6, asr #5
- eor r4, r5, r6, ror #5
- eor r6, r7, r8, lsl r9
- eor r6, r7, r8, lsr r9
- eor r6, r7, r8, asr r9
- eor r6, r7, r8, ror r9
- eor r4, r5, r6, rrx
-
- @ destination register is optional
- eor r5, #0xf000
- eor r4, r5
- eor r4, r5, lsl #5
- eor r4, r5, lsr #5
- eor r4, r5, lsr #5
- eor r4, r5, asr #5
- eor r4, r5, ror #5
- eor r6, r7, lsl r9
- eor r6, r7, lsr r9
- eor r6, r7, asr r9
- eor r6, r7, ror r9
- eor r4, r5, rrx
+ eor r4, r5, #0xf000
+ eor r4, r5, r6
+ eor r4, r5, r6, lsl #5
+ eor r4, r5, r6, lsr #5
+ eor r4, r5, r6, lsr #5
+ eor r4, r5, r6, asr #5
+ eor r4, r5, r6, ror #5
+ eor r6, r7, r8, lsl r9
+ eor r6, r7, r8, lsr r9
+ eor r6, r7, r8, asr r9
+ eor r6, r7, r8, ror r9
+ eor r4, r5, r6, rrx
+
+ @ destination register is optional
+ eor r5, #0xf000
+ eor r4, r5
+ eor r4, r5, lsl #5
+ eor r4, r5, lsr #5
+ eor r4, r5, lsr #5
+ eor r4, r5, asr #5
+ eor r4, r5, ror #5
+ eor r6, r7, lsl r9
+ eor r6, r7, lsr r9
+ eor r6, r7, asr r9
+ eor r6, r7, ror r9
+ eor r4, r5, rrx
@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2]
@ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0]
@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
-@------------------------------------------------------------------------------
-@ FIXME: LDR*
-@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
@ LDREX/LDREXB/LDREXH/LDREXD
@ CHECK: ldrex r1, [r7] @ encoding: [0x9f,0x1f,0x97,0xe1]
@ CHECK: ldrexd r6, r7, [r8] @ encoding: [0x9f,0x6f,0xb8,0xe1]
+@------------------------------------------------------------------------------
+@ LDRHT
+@------------------------------------------------------------------------------
+ ldrhthi r8, [r11], #-0
+ ldrhthi r8, [r11], #0
+
+@ CHECK: ldrhthi r8, [r11], #-0 @ encoding: [0xb0,0x80,0x7b,0x80]
+@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80]
@------------------------------------------------------------------------------
@ FIXME: LSL
@------------------------------------------------------------------------------
@ MOV (immediate)
@------------------------------------------------------------------------------
- mov r3, #7
- mov r4, #0xff0
- mov r5, #0xff0000
- mov r6, #0xffff
- movw r9, #0xffff
- movs r3, #7
- moveq r4, #0xff0
- movseq r5, #0xff0000
+ mov r3, #7
+ mov r4, #0xff0
+ mov r5, #0xff0000
+ mov r6, #0xffff
+ movw r9, #0xffff
+ movs r3, #7
+ moveq r4, #0xff0
+ movseq r5, #0xff0000
@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
@------------------------------------------------------------------------------
@ MOVT
@------------------------------------------------------------------------------
- movt r3, #7
- movt r6, #0xffff
- movteq r4, #0xff0
+ movt r3, #7
+ movt r6, #0xffff
+ movteq r4, #0xff0
@ CHECK: movt r3, #7 @ encoding: [0x07,0x30,0x40,0xe3]
@ CHECK: movt r6, #65535 @ encoding: [0xff,0x6f,0x4f,0xe3]
msr SPSR_fsxc, #5
msr cpsr_fsxc, #5
-@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3]
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
msr SPSR_fsxc, r0
msr cpsr_fsxc, r0
-@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
@ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
@------------------------------------------------------------------------------
@ MUL
@------------------------------------------------------------------------------
-
- mul r5, r6, r7
- muls r5, r6, r7
- mulgt r5, r6, r7
- mulsle r5, r6, r7
+ mul r5, r6, r7
+ muls r5, r6, r7
+ mulgt r5, r6, r7
+ mulsle r5, r6, r7
@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0]
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
@------------------------------------------------------------------------------
@ MVN (immediate)
@------------------------------------------------------------------------------
- mvn r3, #7
- mvn r4, #0xff0
- mvn r5, #0xff0000
- mvns r3, #7
- mvneq r4, #0xff0
- mvnseq r5, #0xff0000
+ mvn r3, #7
+ mvn r4, #0xff0
+ mvn r5, #0xff0000
+ mvns r3, #7
+ mvneq r4, #0xff0
+ mvnseq r5, #0xff0000
@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3]
@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3]
pop {r7}
pop {r7, r8, r9, r10}
-@ FIXME: pop of a single register should encode as "ldr r7, [sp], #4"
-@ CHECK-FIXME: pop {r7} @ encoding: [0x04,0x70,0x9d,0xe4]
+@ CHECK: pop {r7} @ encoding: [0x04,0x70,0x9d,0xe4]
@ CHECK: pop {r7, r8, r9, r10} @ encoding: [0x80,0x07,0xbd,0xe8]
push {r7}
push {r7, r8, r9, r10}
-@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!"
-@ CHECK-FIXME: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
+@ CHECK: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5]
@ CHECK: push {r7, r8, r9, r10} @ encoding: [0x80,0x07,0x2d,0xe9]
rsc r6, r7, r8, lsr r9
rsc r6, r7, r8, asr r9
rscle r6, r7, r8, ror r9
+ rscs r1, r8, #4064
@ destination register is optional
rsc r5, #0xf000
@ CHECK: rsc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xe7,0xe0]
@ CHECK: rsc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xe7,0xe0]
@ CHECK: rscle r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xe7,0xd0]
+@ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2]
@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2]
@ CHECK: rsc r4, r4, r5 @ encoding: [0x05,0x40,0xe4,0xe0]
setend be
setend le
- sel r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0xe6]
- selne r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0x16]
+@ CHECK: setend be @ encoding: [0x00,0x02,0x01,0xf1]
+@ CHECK: setend le @ encoding: [0x00,0x00,0x01,0xf1]
@------------------------------------------------------------------------------
@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9]
-@------------------------------------------------------------------------------
-@ FIXME:STR*
-@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
@ STREX/STREXB/STREXH/STREXD
@------------------------------------------------------------------------------
@ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1]
@ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1]
+@------------------------------------------------------------------------------
+@ STR
+@------------------------------------------------------------------------------
+ strpl r3, [r10, #-0]!
+ strpl r3, [r10, #0]!
+
+@ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55]
+@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55]
@------------------------------------------------------------------------------
@ SUB
@ CHECK: sxtab r2, r3, r4 @ encoding: [0x74,0x20,0xa3,0xe6]
@ CHECK: sxtab r4, r5, r6 @ encoding: [0x76,0x40,0xa5,0xe6]
-@ CHECK: sxtablt r6, r2, r9, ror #8
- @ encoding: [0x79,0x64,0xa2,0xb6]
-@ CHECK: sxtab r5, r1, r4, ror #16
- @ encoding: [0x74,0x58,0xa1,0xe6]
-@ CHECK: sxtab r7, r8, r3, ror #24
- @ encoding: [0x73,0x7c,0xa8,0xe6]
+@ CHECK: sxtablt r6, r2, r9, ror #8 @ encoding: [0x79,0x64,0xa2,0xb6]
+@ CHECK: sxtab r5, r1, r4, ror #16 @ encoding: [0x74,0x58,0xa1,0xe6]
+@ CHECK: sxtab r7, r8, r3, ror #24 @ encoding: [0x73,0x7c,0xa8,0xe6]
@------------------------------------------------------------------------------
@ CHECK: sxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0x81,0xa6]
@ CHECK: sxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0x82,0xe6]
-@ CHECK: sxtab16 r3, r5, r8, ror #8
- @ encoding: [0x78,0x34,0x85,0xe6]
-@ CHECK: sxtab16 r3, r2, r1, ror #16
- @ encoding: [0x71,0x38,0x82,0xe6]
-@ CHECK: sxtab16eq r1, r2, r3, ror #24
- @ encoding: [0x73,0x1c,0x82,0x06]
+@ CHECK: sxtab16 r3, r5, r8, ror #8 @ encoding: [0x78,0x34,0x85,0xe6]
+@ CHECK: sxtab16 r3, r2, r1, ror #16 @ encoding: [0x71,0x38,0x82,0xe6]
+@ CHECK: sxtab16eq r1, r2, r3, ror #24 @ encoding: [0x73,0x1c,0x82,0x06]
@------------------------------------------------------------------------------
@ SXTAH
@ CHECK: sxtah r1, r3, r9 @ encoding: [0x79,0x10,0xb3,0xe6]
@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xb1,0x86]
-@ CHECK: sxtah r3, r8, r3, ror #8
- @ encoding: [0x73,0x34,0xb8,0xe6]
-@ CHECK: sxtahlo r2, r2, r4, ror #16
- @ encoding: [0x74,0x28,0xb2,0x36]
-@ CHECK: sxtah r9, r3, r3, ror #24
- @ encoding: [0x73,0x9c,0xb3,0xe6]
+@ CHECK: sxtah r3, r8, r3, ror #8 @ encoding: [0x73,0x34,0xb8,0xe6]
+@ CHECK: sxtahlo r2, r2, r4, ror #16 @ encoding: [0x74,0x28,0xb2,0x36]
+@ CHECK: sxtah r9, r3, r3, ror #24 @ encoding: [0x73,0x9c,0xb3,0xe6]
@------------------------------------------------------------------------------
@ SXTB
@ CHECK: sxtbge r2, r4 @ encoding: [0x74,0x20,0xaf,0xa6]
@ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6]
-@ CHECK: sxtb r6, r9, ror #8
- @ encoding: [0x79,0x64,0xaf,0xe6]
-@ CHECK: sxtblo r5, r1, ror #16
- @ encoding: [0x71,0x58,0xaf,0x36]
-@ CHECK: sxtb r8, r3, ror #24
- @ encoding: [0x73,0x8c,0xaf,0xe6]
+@ CHECK: sxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xaf,0xe6]
+@ CHECK: sxtblo r5, r1, ror #16 @ encoding: [0x71,0x58,0xaf,0x36]
+@ CHECK: sxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xaf,0xe6]
@------------------------------------------------------------------------------
@ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6]
@ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6]
-@ CHECK: sxtb16hs r3, r5, ror #8
- @ encoding: [0x75,0x34,0x8f,0x26]
-@ CHECK: sxtb16 r3, r1, ror #16
- @ encoding: [0x71,0x38,0x8f,0xe6]
-@ CHECK: sxtb16ge r2, r3, ror #24
- @ encoding: [0x73,0x2c,0x8f,0xa6]
+@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x75,0x34,0x8f,0x26]
+@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0x8f,0xe6]
+@ CHECK: sxtb16ge r2, r3, ror #24 @ encoding: [0x73,0x2c,0x8f,0xa6]
@------------------------------------------------------------------------------
@ CHECK: sxthne r3, r9 @ encoding: [0x79,0x30,0xbf,0x16]
@ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6]
-@ CHECK: sxth r3, r8, ror #8
- @ encoding: [0x78,0x34,0xbf,0xe6]
-@ CHECK: sxthle r2, r2, ror #16
- @ encoding: [0x72,0x28,0xbf,0xd6]
-@ CHECK: sxth r9, r3, ror #24
- @ encoding: [0x73,0x9c,0xbf,0xe6]
+@ CHECK: sxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xbf,0xe6]
+@ CHECK: sxthle r2, r2, ror #16 @ encoding: [0x72,0x28,0xbf,0xd6]
+@ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6]
@------------------------------------------------------------------------------
umaal r3, r4, r5, r6
umaallt r3, r4, r5, r6
-@ CHECK: umaal r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xe0]
-@ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0x95,0x46,0x43,0xb0]
+@ CHECK: umaal r3, r4, r5, r6 @ encoding: [0x95,0x36,0x44,0xe0]
+@ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0x95,0x36,0x44,0xb0]
@------------------------------------------------------------------------------
usat16 r2, #2, r7
usat16 r3, #15, r5
-@ CHECK: usat16 r2, #2, r7 @ encoding: [0x32,0x2f,0xe2,0xe6]
-@ CHECK: usat16 r3, #15, r5 @ encoding: [0x33,0x3f,0xef,0xe6]
+@ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6]
+@ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
@------------------------------------------------------------------------------
@ CHECK: uxtab r2, r3, r4 @ encoding: [0x74,0x20,0xe3,0xe6]
@ CHECK: uxtab r4, r5, r6 @ encoding: [0x76,0x40,0xe5,0xe6]
-@ CHECK: uxtablt r6, r2, r9, ror #8
- @ encoding: [0x79,0x64,0xe2,0xb6]
-@ CHECK: uxtab r5, r1, r4, ror #16
- @ encoding: [0x74,0x58,0xe1,0xe6]
-@ CHECK: uxtab r7, r8, r3, ror #24
- @ encoding: [0x73,0x7c,0xe8,0xe6]
+@ CHECK: uxtablt r6, r2, r9, ror #8 @ encoding: [0x79,0x64,0xe2,0xb6]
+@ CHECK: uxtab r5, r1, r4, ror #16 @ encoding: [0x74,0x58,0xe1,0xe6]
+@ CHECK: uxtab r7, r8, r3, ror #24 @ encoding: [0x73,0x7c,0xe8,0xe6]
@------------------------------------------------------------------------------
@ CHECK: uxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0xc1,0xa6]
@ CHECK: uxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0xc2,0xe6]
-@ CHECK: uxtab16 r3, r5, r8, ror #8
- @ encoding: [0x78,0x34,0xc5,0xe6]
-@ CHECK: uxtab16 r3, r2, r1, ror #16
- @ encoding: [0x71,0x38,0xc2,0xe6]
-@ CHECK: uxtab16eq r1, r2, r3, ror #24
- @ encoding: [0x73,0x1c,0xc2,0x06]
+@ CHECK: uxtab16 r3, r5, r8, ror #8 @ encoding: [0x78,0x34,0xc5,0xe6]
+@ CHECK: uxtab16 r3, r2, r1, ror #16 @ encoding: [0x71,0x38,0xc2,0xe6]
+@ CHECK: uxtab16eq r1, r2, r3, ror #24 @ encoding: [0x73,0x1c,0xc2,0x06]
@------------------------------------------------------------------------------
@ UXTAH
@ CHECK: uxtah r1, r3, r9 @ encoding: [0x79,0x10,0xf3,0xe6]
@ CHECK: uxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xf1,0x86]
-@ CHECK: uxtah r3, r8, r3, ror #8
- @ encoding: [0x73,0x34,0xf8,0xe6]
-@ CHECK: uxtahlo r2, r2, r4, ror #16
- @ encoding: [0x74,0x28,0xf2,0x36]
-@ CHECK: uxtah r9, r3, r3, ror #24
- @ encoding: [0x73,0x9c,0xf3,0xe6]
+@ CHECK: uxtah r3, r8, r3, ror #8 @ encoding: [0x73,0x34,0xf8,0xe6]
+@ CHECK: uxtahlo r2, r2, r4, ror #16 @ encoding: [0x74,0x28,0xf2,0x36]
+@ CHECK: uxtah r9, r3, r3, ror #24 @ encoding: [0x73,0x9c,0xf3,0xe6]
@------------------------------------------------------------------------------
@ UXTB
@ CHECK: uxtbge r2, r4 @ encoding: [0x74,0x20,0xef,0xa6]
@ CHECK: uxtb r5, r6 @ encoding: [0x76,0x50,0xef,0xe6]
-@ CHECK: uxtb r6, r9, ror #8
- @ encoding: [0x79,0x64,0xef,0xe6]
-@ CHECK: uxtblo r5, r1, ror #16
- @ encoding: [0x71,0x58,0xef,0x36]
-@ CHECK: uxtb r8, r3, ror #24
- @ encoding: [0x73,0x8c,0xef,0xe6]
+@ CHECK: uxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xef,0xe6]
+@ CHECK: uxtblo r5, r1, ror #16 @ encoding: [0x71,0x58,0xef,0x36]
+@ CHECK: uxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xef,0xe6]
@------------------------------------------------------------------------------
@ CHECK: uxtb16 r1, r4 @ encoding: [0x74,0x10,0xcf,0xe6]
@ CHECK: uxtb16 r6, r7 @ encoding: [0x77,0x60,0xcf,0xe6]
-@ CHECK: uxtb16hs r3, r5, ror #8
- @ encoding: [0x75,0x34,0xcf,0x26]
-@ CHECK: uxtb16 r3, r1, ror #16
- @ encoding: [0x71,0x38,0xcf,0xe6]
-@ CHECK: uxtb16ge r2, r3, ror #24
- @ encoding: [0x73,0x2c,0xcf,0xa6]
+@ CHECK: uxtb16hs r3, r5, ror #8 @ encoding: [0x75,0x34,0xcf,0x26]
+@ CHECK: uxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0xcf,0xe6]
+@ CHECK: uxtb16ge r2, r3, ror #24 @ encoding: [0x73,0x2c,0xcf,0xa6]
@------------------------------------------------------------------------------
@ CHECK: uxthne r3, r9 @ encoding: [0x79,0x30,0xff,0x16]
@ CHECK: uxth r1, r6 @ encoding: [0x76,0x10,0xff,0xe6]
-@ CHECK: uxth r3, r8, ror #8
- @ encoding: [0x78,0x34,0xff,0xe6]
-@ CHECK: uxthle r2, r2, ror #16
- @ encoding: [0x72,0x28,0xff,0xd6]
-@ CHECK: uxth r9, r3, ror #24
- @ encoding: [0x73,0x9c,0xff,0xe6]
+@ CHECK: uxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xff,0xe6]
+@ CHECK: uxthle r2, r2, ror #16 @ encoding: [0x72,0x28,0xff,0xd6]
+@ CHECK: uxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xff,0xe6]
@------------------------------------------------------------------------------
@ WFE/WFI/YIELD
projects / oota-llvm.git / blobdiff