ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.

[oota-llvm.git] / test / MC / ARM / basic-arm-instructions.s

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 861d50faa69de1db8ea20abffc004ec7dfb78e18..fa528467bcf6abac1a4738b736c1fcdd8dc07c8d 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1300,6 +1300,7 @@ Lforward:
         rsc r6, r7, r8, lsr r9
         rsc r6, r7, r8, asr r9
         rscle r6, r7, r8, ror r9
+        rscs r1, r8, #4064
 
         @ destination register is optional
         rsc r5, #0xf000
@@ -1325,6 +1326,7 @@ Lforward:
 @ CHECK: rsc   r6, r7, r8, lsr r9      @ encoding: [0x38,0x69,0xe7,0xe0]
 @ CHECK: rsc   r6, r7, r8, asr r9      @ encoding: [0x58,0x69,0xe7,0xe0]
 @ CHECK: rscle r6, r7, r8, ror r9      @ encoding: [0x78,0x69,0xe7,0xd0]
+@ CHECK: rscs  r1, r8, #4064           @ encoding: [0xfe,0x1e,0xf8,0xe2]
 
 @ CHECK: rsc   r5, r5, #61440          @ encoding: [0x0f,0x5a,0xe5,0xe2]
 @ CHECK: rsc   r4, r4, r5              @ encoding: [0x05,0x40,0xe4,0xe0]