Thumb2 assembly parsing and encoding for UQADD16/UQADD8.

[oota-llvm.git] / test / MC / ARM / basic-thumb-instructions.s

diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index f65c7cc35e4c95ca189219c1e1ef027d6dbf39b0..0fa52b098746505cdc37ef468fef34da26f2fe77 100644 (file)
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -1,4 +1,9 @@
+@---
+@ Run these test in both Thumb1 and Thumb2 modes, as all of the encodings
+@ should be valid, and parse the same, in both.
+@---
 @ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
   .syntax unified
   .globl _func
 
@@ -26,11 +31,13 @@ _func:
 @ ADD (immediate)
 @------------------------------------------------------------------------------
         adds r1, r2, #3
+@ When Rd is not explicitly specified, encoding T2 is preferred even though
+@ the literal is in the range [0,7] which would allow encoding T1.
         adds r2, #3
         adds r2, #8
 
 @ CHECK: adds  r1, r2, #3              @ encoding: [0xd1,0x1c]
-@ CHECK: adds  r2, r2, #3              @ encoding: [0xd2,0x1c]
+@ CHECK: adds  r2, #3                  @ encoding: [0x03,0x32]
 @ CHECK: adds  r2, #8                  @ encoding: [0x08,0x32]
 
 
@@ -45,21 +52,40 @@ _func:
 
 
 @------------------------------------------------------------------------------
-@ FIXME: ADD (SP plus immediate)
+@ ADD (SP plus immediate)
 @------------------------------------------------------------------------------
+        add sp, #4
+        add sp, #508
+        add sp, sp, #4
+        add r2, sp, #8
+        add r2, sp, #1020
+
+@ CHECK: add   sp, #4                  @ encoding: [0x01,0xb0]
+@ CHECK: add   sp, #508                @ encoding: [0x7f,0xb0]
+@ CHECK: add   sp, #4                  @ encoding: [0x01,0xb0]
+@ CHECK: add   r2, sp, #8              @ encoding: [0x02,0xaa]
+@ CHECK: add   r2, sp, #1020           @ encoding: [0xff,0xaa]
+
+
 @------------------------------------------------------------------------------
-@ FIXME: ADD (SP plus register)
+@ ADD (SP plus register)
 @------------------------------------------------------------------------------
+        add sp, r3
+        add r2, sp, r2
+
+@ CHECK: add   sp, r3                  @ encoding: [0x9d,0x44]
+@ CHECK: add   r2, sp, r2              @ encoding: [0x6a,0x44]
 
 
 @------------------------------------------------------------------------------
 @ ADR
 @------------------------------------------------------------------------------
         adr r2, _baz
+        adr    r2, #3
 
 @ CHECK: adr   r2, _baz                @ encoding: [A,0xa2]
             @   fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
-
+@ CHECK: adr   r2, #3                  @ encoding: [0x03,0xa2]
 
 @------------------------------------------------------------------------------
 @ ASR (immediate)
@@ -86,12 +112,28 @@ _func:
 @------------------------------------------------------------------------------
         b _baz
         beq _bar
+        b       #1838
+        b       #-420
+        beq     #336
+        beq     #160
 
 @ CHECK: b     _baz                    @ encoding: [A,0xe0'A']
              @   fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
 @ CHECK: beq   _bar                    @ encoding: [A,0xd0]
              @   fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
+@ CHECK: b       #1838                   @ encoding: [0x97,0xe3]
+@ CHECK: b       #-420                   @ encoding: [0x2e,0xe7]
+@ CHECK: beq     #336                    @ encoding: [0xa8,0xd0]
+@ CHECK: beq     #160                    @ encoding: [0x50,0xd0]
+
+@------------------------------------------------------------------------------
+@ BL/BLX
+@------------------------------------------------------------------------------
+        blx     #884800
+        blx     #1769600
 
+@ CHECK: blx     #884800                 @ encoding: [0xd8,0xf0,0x20,0xe8]
+@ CHECK: blx     #1769600                @ encoding: [0xb0,0xf1,0x40,0xe8]
 
 @------------------------------------------------------------------------------
 @ BICS
@@ -202,10 +244,13 @@ _func:
 @ LDR (literal)
 @------------------------------------------------------------------------------
         ldr r1, _foo
+        ldr     r3, #604
+        ldr     r3, #368
 
 @ CHECK: ldr   r1, _foo                @ encoding: [A,0x49]
              @   fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
-
+@ CHECK: ldr     r3, #604                @ encoding: [0x97,0x4b]
+@ CHECK: ldr     r3, #368                @ encoding: [0x5c,0x4b]
 
 @------------------------------------------------------------------------------
 @ LDR (register)
@@ -348,15 +393,6 @@ _func:
 
 @ CHECK: rsbs  r3, r4, #0              @ encoding: [0x63,0x42]
 
-
-@------------------------------------------------------------------------------
-@ NOP
-@------------------------------------------------------------------------------
-        nop
-
-@ CHECK: nop                            @ encoding: [0xc0,0x46]
-
-
 @------------------------------------------------------------------------------
 @ ORR
 @------------------------------------------------------------------------------
@@ -520,11 +556,13 @@ _func:
 
 
 @------------------------------------------------------------------------------
-@ FIXME: SUB (SP minus immediate)
-@------------------------------------------------------------------------------
-@------------------------------------------------------------------------------
-@ FIXME: SUB (SP minus register)
+@ SUB (SP minus immediate)
 @------------------------------------------------------------------------------
+        sub sp, #12
+        sub sp, sp, #508
+
+@ CHECK: sub   sp, #12                 @ encoding: [0x83,0xb0]
+@ CHECK: sub   sp, #508                @ encoding: [0xff,0xb0]
 
 
 @------------------------------------------------------------------------------
@@ -561,3 +599,25 @@ _func:
         tst r6, r1
 
 @ CHECK: tst   r6, r1                  @ encoding: [0x0e,0x42]
+
+
+@------------------------------------------------------------------------------
+@ UXTB/UXTH
+@------------------------------------------------------------------------------
+        uxtb  r7, r2
+        uxth  r1, r4
+
+@ CHECK: uxtb  r7, r2                  @ encoding: [0xd7,0xb2]
+@ CHECK: uxth  r1, r4                  @ encoding: [0xa1,0xb2]
+
+
+@------------------------------------------------------------------------------
+@ WFE/WFI/YIELD
+@------------------------------------------------------------------------------
+        wfe
+        wfi
+        yield
+
+@ CHECK: wfe                             @ encoding: [0x20,0xbf]
+@ CHECK: wfi                             @ encoding: [0x30,0xbf]
+@ CHECK: yield                           @ encoding: [0x10,0xbf]