ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb...

[oota-llvm.git] / test / MC / ARM / neon-mul-encoding.s

diff --git a/test/MC/ARM/neon-mul-encoding.s b/test/MC/ARM/neon-mul-encoding.s
index 990187e78212806961d70bb112055389a8f7d8fd..d6bc1f3291f3a16bc2466daec2a90d3d9c6e0928 100644 (file)
--- a/test/MC/ARM/neon-mul-encoding.s
+++ b/test/MC/ARM/neon-mul-encoding.s
@@ -1,6 +1,5 @@
 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
 
-
        vmul.i8 d16, d16, d17
        vmul.i16        d16, d16, d17
        vmul.i32        d16, d16, d17
@@ -13,6 +12,17 @@
        vmul.p8 q8, q8, q9
        vmul.i16        d18, d8, d0[3]
 
+       vmul.i8 d16, d17
+       vmul.i16        d16, d17
+       vmul.i32        d16, d17
+       vmul.f32        d16, d17
+       vmul.i8 q8, q9
+       vmul.i16        q8, q9
+       vmul.i32        q8, q9
+       vmul.f32        q8, q9
+       vmul.p8 d16, d17
+       vmul.p8 q8, q9
+
 @ CHECK: vmul.i8       d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf2]
 @ CHECK: vmul.i16      d16, d16, d17   @ encoding: [0xb1,0x09,0x50,0xf2]
 @ CHECK: vmul.i32      d16, d16, d17   @ encoding: [0xb1,0x09,0x60,0xf2]
@@ -25,13 +35,32 @@
 @ CHECK: vmul.p8       q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf3]
 @ CHECK: vmul.i16      d18, d8, d0[3]  @ encoding: [0x68,0x28,0xd8,0xf2]
 
+@ CHECK: vmul.i8       d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf2]
+@ CHECK: vmul.i16      d16, d16, d17   @ encoding: [0xb1,0x09,0x50,0xf2]
+@ CHECK: vmul.i32      d16, d16, d17   @ encoding: [0xb1,0x09,0x60,0xf2]
+@ CHECK: vmul.f32      d16, d16, d17   @ encoding: [0xb1,0x0d,0x40,0xf3]
+@ CHECK: vmul.i8       q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf2]
+@ CHECK: vmul.i16      q8, q8, q9      @ encoding: [0xf2,0x09,0x50,0xf2]
+@ CHECK: vmul.i32      q8, q8, q9      @ encoding: [0xf2,0x09,0x60,0xf2]
+@ CHECK: vmul.f32      q8, q8, q9      @ encoding: [0xf2,0x0d,0x40,0xf3]
+@ CHECK: vmul.p8       d16, d16, d17   @ encoding: [0xb1,0x09,0x40,0xf3]
+@ CHECK: vmul.p8       q8, q8, q9      @ encoding: [0xf2,0x09,0x40,0xf3]
+
 
        vqdmulh.s16     d16, d16, d17
        vqdmulh.s32     d16, d16, d17
        vqdmulh.s16     q8, q8, q9
        vqdmulh.s32     q8, q8, q9
+       vqdmulh.s16     d16, d17
+       vqdmulh.s32     d16, d17
+       vqdmulh.s16     q8, q9
+       vqdmulh.s32     q8, q9
        vqdmulh.s16     d11, d2, d3[0]
 
+@ CHECK: vqdmulh.s16   d16, d16, d17   @ encoding: [0xa1,0x0b,0x50,0xf2]
+@ CHECK: vqdmulh.s32   d16, d16, d17   @ encoding: [0xa1,0x0b,0x60,0xf2]
+@ CHECK: vqdmulh.s16   q8, q8, q9      @ encoding: [0xe2,0x0b,0x50,0xf2]
+@ CHECK: vqdmulh.s32   q8, q8, q9      @ encoding: [0xe2,0x0b,0x60,0xf2]
 @ CHECK: vqdmulh.s16   d16, d16, d17   @ encoding: [0xa1,0x0b,0x50,0xf2]
 @ CHECK: vqdmulh.s32   d16, d16, d17   @ encoding: [0xa1,0x0b,0x60,0xf2]
 @ CHECK: vqdmulh.s16   q8, q8, q9      @ encoding: [0xe2,0x0b,0x50,0xf2]