[PowerPC] Implement writeNopData

[oota-llvm.git] / test / MC / ARM / neon-shift-encoding.s

diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s
index c49daf7361b30c274f0dc76db560fa2003c1979d..3c97f8b61fb3f78059dabe176fec0d6f15338262 100644 (file)
--- a/test/MC/ARM/neon-shift-encoding.s
+++ b/test/MC/ARM/neon-shift-encoding.s
@@ -429,6 +429,41 @@ _foo:
 @ CHECK: vshl.i32      d4, d4, #17     @ encoding: [0x14,0x45,0xb1,0xf2]
 @ CHECK: vshl.i64      d4, d4, #43     @ encoding: [0x94,0x45,0xab,0xf2]
 
+        @ Two-operand VRSHL forms.
+       vrshl.s8        d11, d4
+       vrshl.s16       d12, d5
+       vrshl.s32       d13, d6
+       vrshl.s64       d14, d7
+       vrshl.u8        d15, d8
+       vrshl.u16       d16, d9
+       vrshl.u32       d17, d10
+       vrshl.u64       d18, d11
+       vrshl.s8        q1, q8
+       vrshl.s16       q2, q15
+       vrshl.s32       q3, q14
+       vrshl.s64       q4, q13
+       vrshl.u8        q5, q12
+       vrshl.u16       q6, q11
+       vrshl.u32       q7, q10
+       vrshl.u64       q8, q9
+
+@ CHECK: vrshl.s8      d11, d11, d4    @ encoding: [0x0b,0xb5,0x04,0xf2]
+@ CHECK: vrshl.s16     d12, d12, d5    @ encoding: [0x0c,0xc5,0x15,0xf2]
+@ CHECK: vrshl.s32     d13, d13, d6    @ encoding: [0x0d,0xd5,0x26,0xf2]
+@ CHECK: vrshl.s64     d14, d14, d7    @ encoding: [0x0e,0xe5,0x37,0xf2]
+@ CHECK: vrshl.u8      d15, d15, d8    @ encoding: [0x0f,0xf5,0x08,0xf3]
+@ CHECK: vrshl.u16     d16, d16, d9    @ encoding: [0x20,0x05,0x59,0xf3]
+@ CHECK: vrshl.u32     d17, d17, d10   @ encoding: [0x21,0x15,0x6a,0xf3]
+@ CHECK: vrshl.u64     d18, d18, d11   @ encoding: [0x22,0x25,0x7b,0xf3]
+@ CHECK: vrshl.s8      q1, q1, q8      @ encoding: [0xc2,0x25,0x00,0xf2]
+@ CHECK: vrshl.s16     q2, q2, q15     @ encoding: [0xc4,0x45,0x1e,0xf2]
+@ CHECK: vrshl.s32     q3, q3, q14     @ encoding: [0xc6,0x65,0x2c,0xf2]
+@ CHECK: vrshl.s64     q4, q4, q13     @ encoding: [0xc8,0x85,0x3a,0xf2]
+@ CHECK: vrshl.u8      q5, q5, q12     @ encoding: [0xca,0xa5,0x08,0xf3]
+@ CHECK: vrshl.u16     q6, q6, q11     @ encoding: [0xcc,0xc5,0x16,0xf3]
+@ CHECK: vrshl.u32     q7, q7, q10     @ encoding: [0xce,0xe5,0x24,0xf3]
+@ CHECK: vrshl.u64     q8, q8, q9      @ encoding: [0xe0,0x05,0x72,0xf3]
+
 
 @ Two-operand forms.
        vshr.s8 d15, #8