ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb...

[oota-llvm.git] / test / MC / ARM / thumb-diagnostics.s

diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s
index 1c7db6323b51c5090e40fdbf6995f04a4147628d..6f822d1c8e8ad7addc4e4d41cbcff4e269a03a6b 100644 (file)
--- a/test/MC/ARM/thumb-diagnostics.s
+++ b/test/MC/ARM/thumb-diagnostics.s
@@ -24,13 +24,9 @@
 
 @ Out of range immediates for ASR instruction.
         asrs r2, r3, #33
-        asrs r2, r3, #0
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         asrs r2, r3, #33
 @ CHECK-ERRORS:                      ^
-@ CHECK-ERRORS: error: invalid operand for instruction
-@ CHECK-ERRORS:         asrs r2, r3, #0
-@ CHECK-ERRORS:                      ^
 
 @ Out of range immediates for BKPT instruction.
         bkpt #256
@@ -57,6 +53,27 @@ error: invalid operand for instruction
 @ CHECK-ERRORS:               ^
 
 
+@ Invalid writeback and register lists for PUSH/POP
+        pop {r1, r2, r10}
+        push {r8, r9}
+@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
+@ CHECK-ERRORS:         pop {r1, r2, r10}
+@ CHECK-ERRORS:             ^
+@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
+@ CHECK-ERRORS:         push {r8, r9}
+@ CHECK-ERRORS:              ^
+
+
+@ Invalid writeback and register lists for STM
+        stm r1, {r2, r6}
+        stm r1!, {r2, r9}
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         stm r1, {r2, r6}
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: registers must be in range r0-r7
+@ CHECK-ERRORS:         stm r1!, {r2, r9}
+@ CHECK-ERRORS:                  ^
+
 @ Out of range immediates for LSL instruction.
         lsls r4, r5, #-1
         lsls r4, r5, #32
@@ -72,3 +89,70 @@ error: invalid operand for instruction
 @ CHECK-ERRORS: error: destination register must match source register
 @ CHECK-ERRORS:         muls r1, r2, r3
 @ CHECK-ERRORS:              ^
+
+
+@ Out of range immediates for STR instruction.
+        str r2, [r7, #-1]
+        str r5, [r1, #3]
+        str r3, [r7, #128]
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         str r2, [r7, #-1]
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         str r5, [r1, #3]
+@ CHECK-ERRORS:         ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         str r3, [r7, #128]
+@ CHECK-ERRORS:         ^
+
+@ Out of range immediate for SVC instruction.
+        svc #-1
+        svc #256
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS:         svc #-1
+@ CHECK-ERRORS:             ^
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS:         svc #256
+@ CHECK-ERRORS:         ^
+
+
+@ Out of range immediate for ADD SP instructions
+        add sp, #-1
+        add sp, #3
+        add sp, sp, #512
+        add r2, sp, #1024
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         add sp, #-1
+@ CHECK-ERRORS:                 ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         add sp, #3
+@ CHECK-ERRORS:                 ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS:         add sp, sp, #512
+@ CHECK-ERRORS:                     ^
+@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS:         add r2, sp, #1024
+@ CHECK-ERRORS:         ^
+
+        add r2, sp, ip
+@ CHECK-ERRORS: error: source register must be the same as destination
+@ CHECK-ERRORS:         add r2, sp, ip
+@ CHECK-ERRORS:                     ^
+ 
+@------------------------------------------------------------------------------
+@ WFE/WFI/YIELD - are not supported pre v6T2
+@------------------------------------------------------------------------------
+        wfe
+        wfi
+        yield
+
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS: wfe
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS: wfi
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires: thumb2
+@ CHECK-ERRORS: yield
+@ CHECK-ERRORS: ^
+