@ CHECK-ERRORS: ^
+@ Invalid writeback and register lists for STM
+ stm r1, {r2, r6}
+ stm r1!, {r2, r9}
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: stm r1, {r2, r6}
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: registers must be in range r0-r7
+@ CHECK-ERRORS: stm r1!, {r2, r9}
+@ CHECK-ERRORS: ^
@ Out of range immediates for LSL instruction.
lsls r4, r5, #-1
@ CHECK-ERRORS: error: destination register must match source register
@ CHECK-ERRORS: muls r1, r2, r3
@ CHECK-ERRORS: ^
+
+
+@ Out of range immediates for STR instruction.
+ str r2, [r7, #-1]
+ str r5, [r1, #3]
+ str r3, [r7, #128]
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: str r2, [r7, #-1]
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: str r5, [r1, #3]
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: str r3, [r7, #128]
+@ CHECK-ERRORS: ^
+
+@ Out of range immediate for SVC instruction.
+ svc #-1
+ svc #256
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: svc #-1
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: svc #256
+@ CHECK-ERRORS: ^
+
+
+@ Out of range immediate for ADD SP instructions
+ add sp, #-1
+ add sp, #3
+ add sp, sp, #512
+ add r2, sp, #1024
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: add sp, #-1
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: add sp, #3
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: add sp, sp, #512
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
+@ CHECK-ERRORS: add r2, sp, #1024
+@ CHECK-ERRORS: ^