[ARM] Allow SP in rGPR, starting from ARMv8

[oota-llvm.git] / test / MC / Disassembler / ARM / thumb-v8.txt

diff --git a/test/MC/Disassembler/ARM/thumb-v8.txt b/test/MC/Disassembler/ARM/thumb-v8.txt
index 075b17c9a2aa6d7e066b7250fa067f509e1cef4b..1bcf654a4795fcf8b5b03b612e3f2fc984271a65 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb-v8.txt
+++ b/test/MC/Disassembler/ARM/thumb-v8.txt
@@ -1,4 +1,5 @@
-# RUN: llvm-mc -disassemble -triple thumbv8 -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s
+# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s
 
 0x80 0xba
 # CHECK: hlt #0
@@ -16,3 +17,20 @@
 
 0x8f 0xf7 0x03 0x80 
 # CHECK: dcps3
+
+0xbf 0xf3 0x59 0x8f
+0xbf 0xf3 0x51 0x8f
+0xbf 0xf3 0x55 0x8f
+0xbf 0xf3 0x5d 0x8f
+
+# CHECK: dmb ishld
+# CHECK: dmb oshld
+# CHECK: dmb nshld
+# CHECK: dmb ld
+
+[0x00 0xf0 0x00 0x0d]
+[0x63 0xeb 0x2d 0x46]
+# CHECK: and sp, r0, #0
+# CHECK: sbc.w r6, r3, sp, asr #16
+
+# STDERR-NOT: warning