[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8...

[oota-llvm.git] / test / MC / Disassembler / ARM / thumb1.txt

diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt
index 5b02a58f0c8f63b13255223bb2468edb07aa5de2..a129abba70fde52d204bdf128c1dd45308d06e50 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb1.txt
+++ b/test/MC/Disassembler/ARM/thumb1.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble -show-encoding < %s | FileCheck %s
 
 #------------------------------------------------------------------------------
 # ADC (register)
@@ -28,6 +28,39 @@
 0xd1 0x18
 0x42 0x44
 
+#------------------------------------------------------------------------------
+# ADD (SP plus immediate)
+#------------------------------------------------------------------------------
+# CHECK: add sp, #508
+# CHECK: add sp, #4
+# CHECK: add r2, sp, #8
+# CHECK: add r2, sp, #1020
+
+0x7f 0xb0
+0x01 0xb0
+0x02 0xaa
+0xff 0xaa
+
+
+#------------------------------------------------------------------------------
+# ADD (SP plus register)
+#------------------------------------------------------------------------------
+# CHECK: add sp, r3
+# CHECK: add r2, sp, r2
+
+0x9d 0x44
+0x6a 0x44
+
+#------------------------------------------------------------------------------
+# ADR
+#------------------------------------------------------------------------------
+# CHECK: adr    r5, #0
+# CHECK: adr    r2, #12
+# CHECK: adr    r3, #1020
+0x00 0xa5
+0x03 0xa2
+0xff 0xa3
+
 #------------------------------------------------------------------------------
 # ASR (immediate)
 #------------------------------------------------------------------------------
@@ -53,6 +86,15 @@
 
 0xb1 0x43
 
+#------------------------------------------------------------------------------
+# B
+#------------------------------------------------------------------------------
+# CHECK: bls     #128                    @ encoding: [0x40,0xd9]
+# CHECK: beq     #-256                   @ encoding: [0x80,0xd0]
+
+0x40 0xd9
+0x80 0xd0
+
 #------------------------------------------------------------------------------
 # BKPT
 #------------------------------------------------------------------------------
@@ -122,6 +164,7 @@
 # CHECK: ldr r1, [sp]
 # CHECK: ldr r2, [sp, #24]
 # CHECK: ldr r3, [sp, #1020]
+# CHECK: ldr r1, [pc, #12]
 
 
 0x29 0x68
@@ -130,4 +173,355 @@
 0x00 0x99
 0x06 0x9a
 0xff 0x9b
+0x03 0x49
+
+#------------------------------------------------------------------------------
+# LDR (register)
+#------------------------------------------------------------------------------
+# CHECK: ldr r1, [r2, r3]
+
+0xd1 0x58
+
+
+#------------------------------------------------------------------------------
+# LDRB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r4, [r3]
+# CHECK: ldrb r5, [r6]
+# CHECK: ldrb r6, [r7, #31]
+
+0x1c 0x78
+0x35 0x78
+0xfe 0x7f
+
+
+#------------------------------------------------------------------------------
+# LDRB (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrb r6, [r4, r5]
+
+0x66 0x5d
+
+
+#------------------------------------------------------------------------------
+# LDRH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r3, [r3]
+# CHECK: ldrh r4, [r6, #2]
+# CHECK: ldrh r5, [r7, #62]
+
+0x1b 0x88
+0x74 0x88
+0xfd 0x8f
+
+#------------------------------------------------------------------------------
+# LDRH (register)
+#------------------------------------------------------------------------------
+# CHECK: ldrh r6, [r2, r6]
+
+0x96 0x5b
+
+
+#------------------------------------------------------------------------------
+# LDRSB/LDRSH
+#------------------------------------------------------------------------------
+# CHECK: ldrsb r6, [r2, r6]
+# CHECK: ldrsh r3, [r7, r1]
+
+0x96 0x57
+0x7b 0x5e
+
+#------------------------------------------------------------------------------
+# LSL (immediate)
+#------------------------------------------------------------------------------
+# CHECK: movs r4, r5
+# CHECK: lsls r4, r5, #4
+
+0x2c 0x00
+0x2c 0x01
+
+
+#------------------------------------------------------------------------------
+# LSL (register)
+#------------------------------------------------------------------------------
+# CHECK: lsls r2, r6
+
+0xb2 0x40
+
+
+#------------------------------------------------------------------------------
+# LSR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: lsrs r1, r3, #1
+# CHECK: lsrs r1, r3, #32
+
+0x59 0x08
+0x19 0x08
+
+
+#------------------------------------------------------------------------------
+# LSR (register)
+#------------------------------------------------------------------------------
+# CHECK: lsrs r2, r6
+
+0xf2 0x40
+
+#------------------------------------------------------------------------------
+# MOV (immediate)
+#------------------------------------------------------------------------------
+# CHECK: movs r2, #0
+# CHECK: movs r2, #255
+# CHECK: movs r2, #23
+
+0x00 0x22
+0xff 0x22
+0x17 0x22
+
+
+#------------------------------------------------------------------------------
+# MOV (register)
+#------------------------------------------------------------------------------
+# CHECK: mov r3, r4
+# CHECK: movs r1, r3
+# CHECK: mov r8, r8
+
+0x23 0x46
+0x19 0x00
+0xc0 0x46
+
+
+#------------------------------------------------------------------------------
+# MUL
+#------------------------------------------------------------------------------
+# CHECK: muls r1, r2, r1
+# CHECK: muls r3, r4
+
+0x51 0x43
+0x63 0x43
+
+
+#------------------------------------------------------------------------------
+# MVN
+#------------------------------------------------------------------------------
+# CHECK: mvns r6, r3
+
+0xde 0x43
+
+#------------------------------------------------------------------------------
+# NEG
+#------------------------------------------------------------------------------
+# CHECK: rsbs r3, r4, #0
+
+0x63 0x42
+
+
+#------------------------------------------------------------------------------
+# ORR
+#------------------------------------------------------------------------------
+# CHECK: orrs  r3, r4
+
+0x23 0x43
+
+#------------------------------------------------------------------------------
+# POP
+#------------------------------------------------------------------------------
+# CHECK: pop {r2, r3, r6}
+
+0x4c 0xbc
+
+
+#------------------------------------------------------------------------------
+# PUSH
+#------------------------------------------------------------------------------
+# CHECK: push {r1, r2, r7}
+
+0x86 0xb4
+
+
+#------------------------------------------------------------------------------
+# REV/REV16/REVSH
+#------------------------------------------------------------------------------
+# CHECK: rev r6, r3
+# CHECK: rev16 r7, r2
+# CHECK: revsh r5, r1
+
+0x1e 0xba
+0x57 0xba
+0xcd 0xba
+
+
+#------------------------------------------------------------------------------
+# ROR
+#------------------------------------------------------------------------------
+# CHECK: rors r2, r7
+
+0xfa 0x41
+
+#------------------------------------------------------------------------------
+# RSB
+#------------------------------------------------------------------------------
+# CHECK: rsbs r1, r3, #0
+
+0x59 0x42
+
+
+#------------------------------------------------------------------------------
+# SBC
+#------------------------------------------------------------------------------
+# CHECK: sbcs r4, r3
+
+0x9c 0x41
+
+
+#------------------------------------------------------------------------------
+# SETEND
+#------------------------------------------------------------------------------
+# CHECK: setend be
+# CHECK: setend le
+
+0x58 0xb6
+0x50 0xb6
+
+#------------------------------------------------------------------------------
+# STM
+#------------------------------------------------------------------------------
+# CHECK: stm r1!, {r2, r6}
+# CHECK: stm r1!, {r1, r2, r3, r7}
+
+0x44 0xc1
+0x8e 0xc1
+
+
+#------------------------------------------------------------------------------
+# STR (immediate)
+#------------------------------------------------------------------------------
+# CHECK: str r2, [r7]
+# CHECK: str r2, [r7]
+# CHECK: str r5, [r1, #4]
+# CHECK: str r3, [r7, #124]
+# CHECK: str r2, [sp]
+# CHECK: str r3, [sp]
+# CHECK: str r4, [sp, #20]
+# CHECK: str r5, [sp, #1020]
+
+0x3a 0x60
+0x3a 0x60
+0x4d 0x60
+0xfb 0x67
+0x00 0x92
+0x00 0x93
+0x05 0x94
+0xff 0x95
+
+
+#------------------------------------------------------------------------------
+# STR (register)
+#------------------------------------------------------------------------------
+# CHECK: str r2, [r7, r3]
+
+0xfa 0x50
+
+
+#------------------------------------------------------------------------------
+# STRB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: strb r4, [r3]
+# CHECK: strb r5, [r6]
+# CHECK: strb r6, [r7, #31]
+
+0x1c 0x70
+0x35 0x70
+0xfe 0x77
+
+
+#------------------------------------------------------------------------------
+# STRB (register)
+#------------------------------------------------------------------------------
+# CHECK: strb r6, [r4, r5]
+
+0x66 0x55
+
+
+#------------------------------------------------------------------------------
+# STRH (immediate)
+#------------------------------------------------------------------------------
+# CHECK: strh r3, [r3]
+# CHECK: strh r4, [r6, #2]
+# CHECK: strh r5, [r7, #62]
+
+0x1b 0x80
+0x74 0x80
+0xfd 0x87
+
+
+#------------------------------------------------------------------------------
+# STRH (register)
+#------------------------------------------------------------------------------
+# CHECK: strh r6, [r2, r6]
+
+0x96 0x53
+
+
+#------------------------------------------------------------------------------
+# SUB (immediate)
+#------------------------------------------------------------------------------
+# CHECK: subs r1, r2, #3
+# CHECK: subs r2, #3
+# CHECK: subs r2, #8
+
+0xd1 0x1e
+0x03 0x3a
+0x08 0x3a
+
+#------------------------------------------------------------------------------
+# SUB (register)
+#------------------------------------------------------------------------------
+# CHECK: subs r1, r2, r3
+
+0xd1 0x1a
+
+#------------------------------------------------------------------------------
+# SUB (SP minus immediate)
+#------------------------------------------------------------------------------
+# CHECK: sub sp, #12
+# CHECK: sub sp, #508
+
+0x83 0xb0
+0xff 0xb0
+
+#------------------------------------------------------------------------------
+# SVC
+#------------------------------------------------------------------------------
+# CHECK: svc #0
+# CHECK: svc #255
+
+0x00 0xdf
+0xff 0xdf
+
+
+#------------------------------------------------------------------------------
+# SXTB/SXTH
+#------------------------------------------------------------------------------
+# CHECK: sxtb r3, r5
+# CHECK: sxth r3, r5
+
+0x6b 0xb2
+0x2b 0xb2
+
+
+#------------------------------------------------------------------------------
+# TST
+#------------------------------------------------------------------------------
+# CHECK: tst r6, r1
+
+0x0e 0x42
+
+
+#------------------------------------------------------------------------------
+# UXTB/UXTH
+#------------------------------------------------------------------------------
+# CHECK: uxtb  r7, r2
+# CHECK: uxth  r1, r4
 
+0xd7 0xb2
+0xa1 0xb2