ARM: Fix pseudo-instructions for SRS (Store Return State).

[oota-llvm.git] / test / MC / Mips / mips-alu-instructions.s

diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index 7384d19e440f4443341b9b4f866825a176c398c8..eccc2880d4167eebc90f1a3dd1b6609d31f000f1 100644 (file)
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -1,13 +1,13 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
 # Check that the assembler can handle the documented syntax
 # for arithmetic and logical instructions.
-# CHECK: .section __TEXT,__text,regular,pure_instructions
 #------------------------------------------------------------------------------
 # Logical instructions
 #------------------------------------------------------------------------------
 # CHECK:  and    $9, $6, $7      # encoding: [0x24,0x48,0xc7,0x00]
 # CHECK:  andi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x30]
 # CHECK:  andi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x30]
+# CHECK:  andi   $9, $9, 17767   # encoding: [0x67,0x45,0x29,0x31]
 # CHECK:  clo    $6, $7          # encoding: [0x21,0x30,0xe6,0x70]
 # CHECK:  clz    $6, $7          # encoding: [0x20,0x30,0xe6,0x70]
 # CHECK:  ins    $19, $9, 6, 7   # encoding: [0x84,0x61,0x33,0x7d]
@@ -15,6 +15,7 @@
 # CHECK:  or     $3, $3, $5      # encoding: [0x25,0x18,0x65,0x00]
 # CHECK:  ori    $4, $5, 17767   # encoding: [0x67,0x45,0xa4,0x34]
 # CHECK:  ori    $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x34]
+# CHECK:  ori    $11, $11, 128   # encoding: [0x80,0x00,0x6b,0x35]
 # CHECK:  rotr   $9, $6, 7       # encoding: [0xc2,0x49,0x26,0x00]
 # CHECK:  rotrv  $9, $6, $7      # encoding: [0x46,0x48,0xe6,0x00]
 # CHECK:  sll    $4, $3, 7       # encoding: [0xc0,0x21,0x03,0x00]
@@ -29,13 +30,15 @@
 # CHECK:  srl    $4, $3, 7       # encoding: [0xc2,0x21,0x03,0x00]
 # CHECK:  srlv   $2, $3, $5      # encoding: [0x06,0x10,0xa3,0x00]
 # CHECK:  xor    $3, $3, $5      # encoding: [0x26,0x18,0x65,0x00]
-# CHECK:  xori    $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x38]
 # CHECK:  xori   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK:  xori   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x38]
+# CHECK:  xori   $11, $11, 12    # encoding: [0x0c,0x00,0x6b,0x39]
 # CHECK:  wsbh   $6, $7          # encoding: [0xa0,0x30,0x07,0x7c]
 # CHECK:  not    $7, $8          # encoding: [0x27,0x38,0x00,0x01]
      and    $9,  $6, $7
      and    $9,  $6, 17767
      andi   $9,  $6, 17767
+     andi   $9,  17767
      clo    $6,  $7
      clz    $6,  $7
      ins    $19, $9, 6,7
@@ -43,6 +46,7 @@
      or     $3,  $3, $5
      or     $4,  $5, 17767
      ori    $9,  $6, 17767
+     ori    $11, 128
      rotr   $9,  $6, 7
      rotrv  $9,  $6, $7
      sll    $4,  $3, 7
@@ -59,6 +63,7 @@
      xor    $3,  $3, $5
      xor    $9,  $6, 17767
      xori   $9,  $6, 17767
+     xori   $11, 12
      wsbh   $6,  $7
      not    $7  ,$8
 
@@ -70,7 +75,9 @@
 # CHECK:  addi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x20]
 # CHECK:  addiu  $9, $6, -15001  # encoding: [0x67,0xc5,0xc9,0x24]
 # CHECK:  addi   $9, $6, 17767   # encoding: [0x67,0x45,0xc9,0x20]
+# CHECK:  addi   $9, $9, 17767   # encoding: [0x67,0x45,0x29,0x21]
 # CHECK:  addiu  $9, $6, -15001  # encoding: [0x67,0xc5,0xc9,0x24]
+# CHECK:  addiu  $11, $11, 40    # encoding: [0x28,0x00,0x6b,0x25]
 # CHECK:  addu   $9, $6, $7      # encoding: [0x21,0x48,0xc7,0x00]
 # CHECK:  madd   $6, $7          # encoding: [0x00,0x00,0xc7,0x70]
 # CHECK:  maddu  $6, $7          # encoding: [0x01,0x00,0xc7,0x70]
@@ -91,7 +98,9 @@
     add    $9,$6,17767
     addu   $9,$6,-15001
     addi   $9,$6,17767
+    addi   $9,17767
     addiu  $9,$6,-15001
+    addiu  $11,40
     addu   $9,$6,$7
     madd   $6,$7
     maddu  $6,$7