ARM: Fix pseudo-instructions for SRS (Store Return State).

[oota-llvm.git] / test / MC / Mips / mips-memory-instructions.s

diff --git a/test/MC/Mips/mips-memory-instructions.s b/test/MC/Mips/mips-memory-instructions.s
index 48678194c5d3b49e73fbe5dfbec46e69145c51b3..c8b055906ebbf0847e75921f69ac451164ff3ed1 100644 (file)
--- a/test/MC/Mips/mips-memory-instructions.s
+++ b/test/MC/Mips/mips-memory-instructions.s
@@ -1,7 +1,6 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
 # Check that the assembler can handle the documented syntax
 # for loads and stores.
-# CHECK: .section __TEXT,__text,regular,pure_instructions
 #------------------------------------------------------------------------------
 # Memory store instructions
 #------------------------------------------------------------------------------
@@ -10,11 +9,15 @@
 # CHECK:  sh      $4, 16($5)      # encoding: [0x10,0x00,0xa4,0xa4]
 # CHECK:  sw      $4, 16($5)      # encoding: [0x10,0x00,0xa4,0xac]
 # CHECK:  sw      $7,  0($5)      # encoding: [0x00,0x00,0xa7,0xac]
+# CHECK:  swc1    $f2, 16($5)     # encoding: [0x10,0x00,0xa2,0xe4]
+# CHECK:  swl     $4, 16($5)      # encoding: [0x10,0x00,0xa4,0xa8]
      sb   $4, 16($5)
      sc   $4, 16($5)
      sh   $4, 16($5)
      sw   $4, 16($5)
      sw   $7,   ($5)
+     swc1 $f2, 16($5)
+     swl  $4, 16($5)
 
 #------------------------------------------------------------------------------
 # Memory load instructions