Fix a FIXME about the format and add a test.

[oota-llvm.git] / test / TableGen / TargetInstrInfo.td

diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td
index 146ef6fd7682630ee4eef7843c59411c197b72ed..e6c563b06aa521d43beaf98b83bf735c3fe15795 100644 (file)
--- a/test/TableGen/TargetInstrInfo.td
+++ b/test/TableGen/TargetInstrInfo.td
@@ -1,6 +1,6 @@
 // This test describes how we eventually want to describe instructions in
 // the target independent code generators.
-// RUN: tblgen %s
+// RUN: llvm-tblgen %s
 // XFAIL: vg_leak
 
 // Target indep stuff.
@@ -110,7 +110,7 @@ def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
                   [(set R32:$dst, (shl R32:$src, CL))]>;
 
 // The RTL list is a list, allowing complex instructions to be defined easily.
-// Temporary 'internal' registers can be used to break instructions appart.
+// Temporary 'internal' registers can be used to break instructions apart.
 let isTwoAddress = 1 in
 def XOR32mi : Inst<(ops addr:$addr, imm32:$imm),
                    "xor $dst, $src2", 0x81, MRM6m,