Add support for code generation of the one register with immediate form of vorr.

[oota-llvm.git] / test / Transforms / GVN / load-pre-align.ll

diff --git a/test/Transforms/GVN/load-pre-align.ll b/test/Transforms/GVN/load-pre-align.ll
index 3a66c0ba62fea157f2a35ca8dbea00d0022329de..d8ad59f9df41c53bae049968e1360c71f1953932 100644 (file)
--- a/test/Transforms/GVN/load-pre-align.ll
+++ b/test/Transforms/GVN/load-pre-align.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 
 @p = external global i32
 
-define arm_apcscc i32 @test(i32 %n) nounwind {
+define i32 @test(i32 %n) nounwind {
 ; CHECK: @test
 entry:
   br label %for.cond