Add support for code generation of the one register with immediate form of vorr.

[oota-llvm.git] / test / Transforms / IndVarSimplify / variable-stride-ivs-0.ll

diff --git a/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll b/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
index 759ba8e177bc9dd4a0e8b3d10433aef900f5c5eb..0c8857f85789ffeed037f9691b4cdb05a48e41e6 100644 (file)
--- a/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
+++ b/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | opt -indvars -instcombine | llvm-dis | \
+; RUN: opt < %s -indvars -instcombine -S | \
 ; RUN:   grep {store i32 0}
 ; Test that -indvars can reduce variable stride IVs.  If it can reduce variable
 ; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without