#include "AsmWriterEmitter.h"
#include "AsmWriterInst.h"
-#include "Error.h"
#include "CodeGenTarget.h"
-#include "Record.h"
#include "StringToOffsetTable.h"
+#include "SequenceToOffsetTable.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
#include <algorithm>
using namespace llvm;
CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
// Build an aggregate string, and build a table of offsets into it.
- StringToOffsetTable StringTable;
+ SequenceToOffsetTable<std::string> StringTable;
/// OpcodeInfo - This encodes the index of the string to use for the first
/// chunk of the output as well as indices used for operand printing.
std::vector<unsigned> OpcodeInfo;
+ // Add all strings to the string table upfront so it can generate an optimized
+ // representation.
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
+ if (AWI != 0 &&
+ AWI->Operands[0].OperandType ==
+ AsmWriterOperand::isLiteralTextOperand &&
+ !AWI->Operands[0].Str.empty()) {
+ std::string Str = AWI->Operands[0].Str;
+ UnescapeString(Str);
+ StringTable.add(Str);
+ }
+ }
+
+ StringTable.layout();
+
unsigned MaxStringIdx = 0;
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
AsmWriterOperand::isLiteralTextOperand ||
AWI->Operands[0].Str.empty()) {
// Something handled by the asmwriter printer, but with no leading string.
- Idx = StringTable.GetOrAddStringOffset("");
+ Idx = StringTable.get("");
} else {
std::string Str = AWI->Operands[0].Str;
UnescapeString(Str);
- Idx = StringTable.GetOrAddStringOffset(Str);
+ Idx = StringTable.get(Str);
MaxStringIdx = std::max(MaxStringIdx, Idx);
// Nuke the string from the operand list. It is now handled!
O << " };\n\n";
// Emit the string itself.
- O << " const char *AsmStrs = \n";
- StringTable.EmitString(O);
- O << ";\n\n";
+ O << " const char AsmStrs[] = {\n";
+ StringTable.emit(O, printChar);
+ O << " };\n\n";
O << " O << \"\\t\";\n\n";
static void
emitRegisterNameString(raw_ostream &O, StringRef AltName,
- const std::vector<CodeGenRegister*> &Registers) {
- StringToOffsetTable StringTable;
- O << " static const unsigned RegAsmOffset" << AltName << "[] = {\n ";
+ const std::vector<CodeGenRegister*> &Registers) {
+ SequenceToOffsetTable<std::string> StringTable;
+ SmallVector<std::string, 4> AsmNames(Registers.size());
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Registers[i];
+ std::string &AsmName = AsmNames[i];
- std::string AsmName;
// "NoRegAltName" is special. We don't need to do a lookup for that,
// as it's just a reference to the default register name.
if (AltName == "" || AltName == "NoRegAltName") {
AsmName = AltNames[Idx];
}
}
+ StringTable.add(AsmName);
+ }
- O << StringTable.GetOrAddStringOffset(AsmName);
- if (((i + 1) % 14) == 0)
- O << ",\n ";
- else
- O << ", ";
+ StringTable.layout();
+ O << " static const char AsmStrs" << AltName << "[] = {\n";
+ StringTable.emit(O, printChar);
+ O << " };\n\n";
+ O << " static const unsigned RegAsmOffset" << AltName << "[] = {";
+ for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+ if ((i % 14) == 0)
+ O << "\n ";
+ O << StringTable.get(AsmNames[i]) << ", ";
}
- O << "0\n"
- << " };\n"
+ O << "\n };\n"
<< "\n";
-
- O << " const char *AsmStrs" << AltName << " =\n";
- StringTable.EmitString(O);
- O << ";\n";
}
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
O << " const unsigned *RegAsmOffset;\n"
<< " const char *AsmStrs;\n"
<< " switch(AltIdx) {\n"
- << " default: assert(0 && \"Invalid register alt name index!\");\n";
+ << " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
StringRef AltName(AltNameIndices[i]->getName());
<< "}\n";
}
-void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
- CodeGenTarget Target(Records);
- Record *AsmWriter = Target.getAsmWriter();
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
- const std::vector<const CodeGenInstruction*> &NumberedInstructions =
- Target.getInstructionsByEnumValue();
-
- StringToOffsetTable StringTable;
- O <<
-"\n\n#ifdef GET_INSTRUCTION_NAME\n"
-"#undef GET_INSTRUCTION_NAME\n\n"
-"/// getInstructionName: This method is automatically generated by tblgen\n"
-"/// from the instruction set description. This returns the enum name of the\n"
-"/// specified instruction.\n"
- "const char *" << Target.getName() << ClassName
- << "::getInstructionName(unsigned Opcode) {\n"
- << " assert(Opcode < " << NumberedInstructions.size()
- << " && \"Invalid instruction number!\");\n"
- << "\n"
- << " static const unsigned InstAsmOffset[] = {";
- for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
- const CodeGenInstruction &Inst = *NumberedInstructions[i];
-
- std::string AsmName = Inst.TheDef->getName();
- if ((i % 14) == 0)
- O << "\n ";
-
- O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
- }
- O << "0\n"
- << " };\n"
- << "\n";
-
- O << " const char *Strs =\n";
- StringTable.EmitString(O);
- O << ";\n";
-
- O << " return Strs+InstAsmOffset[Opcode];\n"
- << "}\n\n#endif\n";
-}
-
namespace {
-
-/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
-/// feature which participates in instruction matching.
-struct SubtargetFeatureInfo {
- /// \brief The predicate record for this feature.
- const Record *TheDef;
-
- /// \brief An unique index assigned to represent this feature.
- unsigned Index;
-
- SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
-
- /// \brief The name of the enumerated constant identifying this feature.
- std::string getEnumName() const {
- return "Feature_" + TheDef->getName();
- }
-};
-
-struct AsmWriterInfo {
- /// Map of Predicate records to their subtarget information.
- std::map<const Record*, SubtargetFeatureInfo*> SubtargetFeatures;
-
- /// getSubtargetFeature - Lookup or create the subtarget feature info for the
- /// given operand.
- SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
- assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
- std::map<const Record*, SubtargetFeatureInfo*>::const_iterator I =
- SubtargetFeatures.find(Def);
- return I == SubtargetFeatures.end() ? 0 : I->second;
- }
-
- void addReqFeatures(const std::vector<Record*> &Features) {
- for (std::vector<Record*>::const_iterator
- I = Features.begin(), E = Features.end(); I != E; ++I) {
- const Record *Pred = *I;
-
- // Ignore predicates that are not intended for the assembler.
- if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
- continue;
-
- if (Pred->getName().empty())
- throw TGError(Pred->getLoc(), "Predicate has no name!");
-
- // Don't add the predicate again.
- if (getSubtargetFeature(Pred))
- continue;
-
- unsigned FeatureNo = SubtargetFeatures.size();
- SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
- assert(FeatureNo < 32 && "Too many subtarget features!");
- }
- }
-
- const SubtargetFeatureInfo *getFeatureInfo(const Record *R) {
- return SubtargetFeatures[R];
- }
-};
-
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
// they both have the same conditionals. In which case, we cannot print out the
// alias for that pattern.
class IAPrinter {
- AsmWriterInfo &AWI;
std::vector<std::string> Conds;
std::map<StringRef, unsigned> OpMap;
std::string Result;
std::string AsmString;
- std::vector<Record*> ReqFeatures;
+ SmallVector<Record*, 4> ReqFeatures;
public:
- IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS)
- : AWI(Info), Result(R), AsmString(AS) {}
+ IAPrinter(std::string R, std::string AS)
+ : Result(R), AsmString(AS) {}
void addCond(const std::string &C) { Conds.push_back(C); }
- void addReqFeatures(const std::vector<Record*> &Features) {
- AWI.addReqFeatures(Features);
- ReqFeatures = Features;
- }
void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
- bool print(raw_ostream &O) {
+ void print(raw_ostream &O) {
if (Conds.empty() && ReqFeatures.empty()) {
O.indent(6) << "return true;\n";
- return false;
+ return;
}
O << "if (";
O << *I;
}
- if (!ReqFeatures.empty()) {
- if (Conds.begin() != Conds.end()) {
- O << " &&\n";
- O.indent(8);
- } else {
- O << "if (";
- }
-
- std::string Req;
- raw_string_ostream ReqO(Req);
-
- for (std::vector<Record*>::iterator
- I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) {
- if (I != ReqFeatures.begin()) ReqO << " | ";
- ReqO << AWI.getFeatureInfo(*I)->getEnumName();
- }
-
- O << "(AvailableFeatures & (" << ReqO.str() << ")) == ("
- << ReqO.str() << ')';
- }
-
O << ") {\n";
O.indent(6) << "// " << Result << "\n";
O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
O.indent(6) << "break;\n";
O.indent(4) << '}';
- return !ReqFeatures.empty();
}
bool operator==(const IAPrinter &RHS) {
} // end anonymous namespace
-/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
-/// definitions.
-static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info,
- raw_ostream &O) {
- O << "namespace {\n\n";
- O << "// Flags for subtarget features that participate in "
- << "alias instruction matching.\n";
- O << "enum SubtargetFeatureFlag {\n";
-
- for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
- I = Info.SubtargetFeatures.begin(),
- E = Info.SubtargetFeatures.end(); I != E; ++I) {
- SubtargetFeatureInfo &SFI = *I->second;
- O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
- }
-
- O << " Feature_None = 0\n";
- O << "};\n\n";
- O << "} // end anonymous namespace\n\n";
-}
-
-/// EmitComputeAvailableFeatures - Emit the function to compute the list of
-/// available features given a subtarget.
-static void EmitComputeAvailableFeatures(AsmWriterInfo &Info,
- Record *AsmWriter,
- CodeGenTarget &Target,
- raw_ostream &O) {
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
- O << "unsigned " << Target.getName() << ClassName << "::\n"
- << "ComputeAvailableFeatures(const " << Target.getName()
- << "Subtarget *Subtarget) const {\n";
- O << " unsigned Features = 0;\n";
-
- for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
- I = Info.SubtargetFeatures.begin(),
- E = Info.SubtargetFeatures.end(); I != E; ++I) {
- SubtargetFeatureInfo &SFI = *I->second;
- O << " if (" << SFI.TheDef->getValueAsString("CondString")
- << ")\n";
- O << " Features |= " << SFI.getEnumName() << ";\n";
- }
-
- O << " return Features;\n";
- O << "}\n\n";
-}
-
static void EmitGetMapOperandNumber(raw_ostream &O) {
O << "static unsigned getMapOperandNumber("
<< "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n";
O << " if (I->first == Name)\n";
O << " return I->second;\n";
- O << " assert(false && \"Operand not in map!\");\n";
- O << " return 0;\n";
- O << "}\n\n";
-}
-
-void AsmWriterEmitter::EmitRegIsInRegClass(raw_ostream &O) {
- CodeGenTarget Target(Records);
-
- // Enumerate the register classes.
- const std::vector<CodeGenRegisterClass> &RegisterClasses =
- Target.getRegisterClasses();
-
- O << "namespace { // Register classes\n";
- O << " enum RegClass {\n";
-
- // Emit the register enum value for each RegisterClass.
- for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
- if (I != 0) O << ",\n";
- O << " RC_" << RegisterClasses[I].TheDef->getName();
- }
-
- O << "\n };\n";
- O << "} // end anonymous namespace\n\n";
-
- // Emit a function that returns 'true' if a regsiter is part of a particular
- // register class. I.e., RAX is part of GR64 on X86.
- O << "static bool regIsInRegisterClass"
- << "(unsigned RegClass, unsigned Reg) {\n";
-
- // Emit the switch that checks if a register belongs to a particular register
- // class.
- O << " switch (RegClass) {\n";
- O << " default: break;\n";
-
- for (unsigned I = 0, E = RegisterClasses.size(); I != E; ++I) {
- const CodeGenRegisterClass &RC = RegisterClasses[I];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
- O << " case RC_" << Name << ":\n";
-
- // Emit the register list now.
- unsigned IE = RC.getOrder().size();
- if (IE == 1) {
- O << " if (Reg == " << getQualifiedName(RC.getOrder()[0]) << ")\n";
- O << " return true;\n";
- } else {
- O << " switch (Reg) {\n";
- O << " default: break;\n";
-
- for (unsigned II = 0; II != IE; ++II) {
- Record *Reg = RC.getOrder()[II];
- O << " case " << getQualifiedName(Reg) << ":\n";
- }
-
- O << " return true;\n";
- O << " }\n";
- }
-
- O << " break;\n";
- }
-
- O << " }\n\n";
- O << " return false;\n";
+ O << " llvm_unreachable(\"Operand not in map!\");\n";
O << "}\n\n";
}
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
O << "#undef PRINT_ALIAS_INSTR\n\n";
- EmitRegIsInRegClass(O);
-
// Emit the method that prints the alias instruction.
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
// A map of which conditions need to be met for each instruction operand
// before it can be matched to the mnemonic.
std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
- AsmWriterInfo AWI;
for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
if (NumResultOps < CountNumOperands(CGA->AsmString))
continue;
- IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(),
+ IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
CGA->AsmString);
- IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates"));
std::string Cond;
Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
switch (RO.Kind) {
- default: assert(0 && "unexpected InstAlias operand kind");
case CodeGenInstAlias::ResultOperand::K_Record: {
const Record *Rec = RO.getRecord();
StringRef ROName = RO.getName();
if (!IAP->isOpMapped(ROName)) {
IAP->addOperand(ROName, i);
- Cond = std::string("regIsInRegisterClass(RC_") +
- CGA->ResultOperands[i].getRecord()->getName() +
- ", MI->getOperand(" + llvm::utostr(i) + ").getReg())";
+ Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
+ CGA->ResultOperands[i].getRecord()->getName() + "RegClassID)"
+ ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())";
IAP->addCond(Cond);
} else {
Cond = std::string("MI->getOperand(") +
IAP->addCond(Cond);
break;
case CodeGenInstAlias::ResultOperand::K_Reg:
+ // If this is zero_reg, something's playing tricks we're not
+ // equipped to handle.
+ if (!CGA->ResultOperands[i].getRegister()) {
+ CantHandle = true;
+ break;
+ }
+
Cond = std::string("MI->getOperand(") +
llvm::utostr(i) + ").getReg() == " + Target.getName() +
"::" + CGA->ResultOperands[i].getRegister()->getName();
}
}
- EmitSubtargetFeatureFlagEnumeration(AWI, O);
- EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O);
-
std::string Header;
raw_string_ostream HeaderO(Header);
std::string Cases;
raw_string_ostream CasesO(Cases);
- bool NeedAvailableFeatures = false;
for (std::map<std::string, std::vector<IAPrinter*> >::iterator
I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
IAPrinter *IAP = *II;
CasesO.indent(4);
- NeedAvailableFeatures |= IAP->print(CasesO);
+ IAP->print(CasesO);
CasesO << '\n';
}
O << HeaderO.str();
O.indent(2) << "StringRef AsmString;\n";
O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
- if (NeedAvailableFeatures)
- O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n";
O.indent(2) << "switch (MI->getOpcode()) {\n";
O.indent(2) << "default: return false;\n";
O << CasesO.str();
O << " }\n";
O << " }\n";
O << " }\n\n";
-
+
O << " return true;\n";
O << "}\n\n";
EmitPrintInstruction(O);
EmitGetRegisterName(O);
- EmitGetInstructionName(O);
EmitPrintAliasInstruction(O);
}
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