Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass...

[oota-llvm.git] / utils / TableGen / CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index 24235381b951a3d455941474ae5cb950b41245bd..a21a31c2bfc123f8d2b1a2d7f96972c4eac3de36 100644 (file)
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -24,7 +24,14 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
        I != E; ++I) {
     Record *R = *I;
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "LABEL" ||
+        R->getName() == "DECLARE" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -49,7 +56,10 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
 }
 
 
-int CodeEmitterGen::getVariableBit(const std::string &VarName, BitsInit *BI, int bit){
+// If the VarBitInit at position 'bit' matches the specified variable then
+// return the variable bit position.  Otherwise return -1.
+int CodeEmitterGen::getVariableBit(const std::string &VarName,
+            BitsInit *BI, int bit) {
   if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
     TypedInit *TI = VBI->getVariable();
     
@@ -90,17 +100,22 @@ void CodeEmitterGen::run(std::ostream &o) {
     
     if (IN != NumberedInstructions.begin()) o << ",\n";
     
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "LABEL" ||
+        R->getName() == "DECLARE" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") {
       o << "    0U";
       continue;
     }
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
-    unsigned Value = 0;
-    const std::vector<RecordVal> &Vals = R->getValues();
-
     // Start by filling in fixed values...
+    unsigned Value = 0;
     for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
       if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(e-i-1))) {
         Value |= B->getValue() << (e-i-1);
@@ -120,11 +135,19 @@ void CodeEmitterGen::run(std::ostream &o) {
     const std::string &InstName = R->getName();
     std::string Case("");
     
-    if (InstName == "PHI" || InstName == "INLINEASM") continue;
+    if (InstName == "PHI" ||
+        InstName == "INLINEASM" ||
+        InstName == "LABEL"||
+        InstName == "DECLARE"||
+        InstName == "EXTRACT_SUBREG" ||
+        InstName == "INSERT_SUBREG" ||
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();
-
+    CodeGenInstruction &CGI = Target.getInstruction(InstName);
+    
     // Loop over all of the fields in the instruction, determining which are the
     // operands to the instruction.
     unsigned op = 0;
@@ -153,10 +176,14 @@ void CodeEmitterGen::run(std::ostream &o) {
             }
 
             if (!gotOp) {
+              /// If this operand is not supposed to be emitted by the generated
+              /// emitter, skip it.
+              while (CGI.isFlatOperandNotEmitted(op))
+                ++op;
+              
               Case += "      // op: " + VarName + "\n"
                    +  "      op = getMachineOpValue(MI, MI.getOperand("
-                   +  utostr(op++)
-                   +  "));\n";
+                   +  utostr(op++) + "));\n";
               gotOp = true;
             }
             
@@ -179,7 +206,7 @@ void CodeEmitterGen::run(std::ostream &o) {
       }
     }
 
-    std::vector<std::string> &InstList =  CaseMap[Case];
+    std::vector<std::string> &InstList = CaseMap[Case];
     InstList.push_back(InstName);
   }
 
@@ -208,7 +235,7 @@ void CodeEmitterGen::run(std::ostream &o) {
 
   // Default case: unhandled opcode
   o << "  default:\n"
-    << "    std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
+    << "    cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
     << "    abort();\n"
     << "  }\n"
     << "  return Value;\n"