Give tablegen's Type a destructor, to suppress spurious

[oota-llvm.git] / utils / TableGen / CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index bc415fcc1db770fb79f556453e94e9a0ab82de41..ae4a6aa445b1ca0f80316202f0a61b2f0751f8e5 100644 (file)
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -24,7 +24,16 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
        I != E; ++I) {
     Record *R = *I;
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "DBG_LABEL" ||
+        R->getName() == "EH_LABEL" ||
+        R->getName() == "GC_LABEL" ||
+        R->getName() == "DECLARE" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -80,7 +89,7 @@ void CodeEmitterGen::run(std::ostream &o) {
 
   // Emit function declaration
   o << "unsigned " << Target.getName() << "CodeEmitter::"
-    << "getBinaryCodeForInstr(MachineInstr &MI) {\n";
+    << "getBinaryCodeForInstr(const MachineInstr &MI) {\n";
 
   // Emit instruction base values
   o << "  static const unsigned InstBits[] = {\n";
@@ -91,10 +100,17 @@ void CodeEmitterGen::run(std::ostream &o) {
     const CodeGenInstruction *CGI = *IN;
     Record *R = CGI->TheDef;
     
-    if (IN != NumberedInstructions.begin()) o << ",\n";
-    
-    if (R->getName() == "PHI" || R->getName() == "INLINEASM") {
-      o << "    0U";
+    if (R->getName() == "PHI" ||
+        R->getName() == "INLINEASM" ||
+        R->getName() == "DBG_LABEL" ||
+        R->getName() == "EH_LABEL" ||
+        R->getName() == "GC_LABEL" ||
+        R->getName() == "DECLARE" ||
+        R->getName() == "EXTRACT_SUBREG" ||
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF" ||
+        R->getName() == "SUBREG_TO_REG") {
+      o << "    0U,\n";
       continue;
     }
     
@@ -107,9 +123,9 @@ void CodeEmitterGen::run(std::ostream &o) {
         Value |= B->getValue() << (e-i-1);
       }
     }
-    o << "    " << Value << "U";
+    o << "    " << Value << "U," << '\t' << "// " << R->getName() << "\n";
   }
-  o << "\n  };\n";
+  o << "    0U\n  };\n";
   
   // Map to accumulate all the cases.
   std::map<std::string, std::vector<std::string> > CaseMap;
@@ -121,11 +137,21 @@ void CodeEmitterGen::run(std::ostream &o) {
     const std::string &InstName = R->getName();
     std::string Case("");
     
-    if (InstName == "PHI" || InstName == "INLINEASM") continue;
+    if (InstName == "PHI" ||
+        InstName == "INLINEASM" ||
+        InstName == "DBG_LABEL"||
+        InstName == "EH_LABEL"||
+        InstName == "GC_LABEL"||
+        InstName == "DECLARE"||
+        InstName == "EXTRACT_SUBREG" ||
+        InstName == "INSERT_SUBREG" ||
+        InstName == "IMPLICIT_DEF" ||
+        InstName == "SUBREG_TO_REG") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();
-
+    CodeGenInstruction &CGI = Target.getInstruction(InstName);
+    
     // Loop over all of the fields in the instruction, determining which are the
     // operands to the instruction.
     unsigned op = 0;
@@ -154,19 +180,18 @@ void CodeEmitterGen::run(std::ostream &o) {
             }
 
             if (!gotOp) {
+              /// If this operand is not supposed to be emitted by the generated
+              /// emitter, skip it.
+              while (CGI.isFlatOperandNotEmitted(op))
+                ++op;
+              
               Case += "      // op: " + VarName + "\n"
                    +  "      op = getMachineOpValue(MI, MI.getOperand("
-                   +  utostr(op++)
-                   +  "));\n";
+                   +  utostr(op++) + "));\n";
               gotOp = true;
-              
-              // If this is a two-address instruction and we just got the dest
-              // op, skip the src op.
-              if (op == 1 && Target.getInstruction(InstName).isTwoAddress)
-                ++op;
             }
             
-            unsigned opMask = (1 << N) - 1;
+            unsigned opMask = ~0U >> (32-N);
             int opShift = beginVarBit - N + 1;
             opMask <<= opShift;
             opShift = beginInstBit - beginVarBit;
@@ -185,7 +210,7 @@ void CodeEmitterGen::run(std::ostream &o) {
       }
     }
 
-    std::vector<std::string> &InstList =  CaseMap[Case];
+    std::vector<std::string> &InstList = CaseMap[Case];
     InstList.push_back(InstName);
   }
 
@@ -193,7 +218,8 @@ void CodeEmitterGen::run(std::ostream &o) {
   // Emit initial function code
   o << "  const unsigned opcode = MI.getOpcode();\n"
     << "  unsigned Value = InstBits[opcode];\n"
-    << "  unsigned op;\n"
+    << "  unsigned op = 0;\n"
+    << "  op = op;  // suppress warning\n"
     << "  switch (opcode) {\n";
 
   // Emit each case statement
@@ -214,7 +240,7 @@ void CodeEmitterGen::run(std::ostream &o) {
 
   // Default case: unhandled opcode
   o << "  default:\n"
-    << "    std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
+    << "    cerr << \"Not supported instr: \" << MI << \"\\n\";\n"
     << "    abort();\n"
     << "  }\n"
     << "  return Value;\n"