std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
unsigned Dim = Indices.size();
ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
- if (Dim != SubRegs->getSize())
+ if (Dim != SubRegs->size())
PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
if (Dim < 2)
PrintFatalError(Def->getLoc(),
// Allocation order 0 is the full set. AltOrders provides others.
const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
ListInit *AltOrders = R->getValueAsListInit("AltOrders");
- Orders.resize(1 + AltOrders->getSize());
+ Orders.resize(1 + AltOrders->size());
// Default allocation order always contains all registers.
for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
// Alternative allocation orders may be subsets.
SetTheory::RecSet Order;
- for (unsigned i = 0, e = AltOrders->getSize(); i != e; ++i) {
+ for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
Orders[1 + i].append(Order.begin(), Order.end());
// Verify that all altorder members are regclass members.
CoveringLanes = ~0u;
for (auto &Idx : SubRegIndices) {
if (Idx.getComposites().empty()) {
+ if (Bit > 32) {
+ PrintFatalError(
+ Twine("Ran out of lanemask bits to represent subregister ")
+ + Idx.getName());
+ }
Idx.LaneMask = 1u << Bit;
- // Share bit 31 in the unlikely case there are more than 32 leafs.
- //
- // Sharing bits is harmless; it allows graceful degradation in targets
- // with more than 32 vector lanes. They simply get a limited resolution
- // view of lanes beyond the 32nd.
- //
- // See also the comment for getSubRegIndexLaneMask().
- if (Bit < 31)
- ++Bit;
- else
- // Once bit 31 is shared among multiple leafs, the 'lane' it represents
- // is no longer covering its registers.
- CoveringLanes &= ~(1u << Bit);
+ ++Bit;
} else {
Idx.LaneMask = 0;
}
continue;
LaneMask |= SubRegIndex.LaneMask;
}
+
+ // For classes without any subregisters set LaneMask to ~0u instead of 0.
+ // This makes it easier for client code to handle classes uniformly.
+ if (LaneMask == 0)
+ LaneMask = ~0u;
+
RegClass.LaneMask = LaneMask;
}
}
&& UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
<< "\n");
+ // We can pick any of the set names for the merged set. Go for the
+ // shortest one to avoid picking the name of one of the classes that are
+ // artificially created by tablegen. So "FPR128_lo" instead of
+ // "QQQQ_with_qsub3_in_FPR128_lo".
+ if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
+ RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
break;
}
}