Implement the last major missing piece in the DAG isel generator: when emitting

[oota-llvm.git] / utils / TableGen / CodeGenTarget.h

diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index 2d65b7be8eaf6ceca2a93e8883f9ea70beceb228..aaa6c7a426f5e0ac53b7def161cba1b852f6bdfb 100644 (file)
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -1,10 +1,10 @@
 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines wrappers for the Target class and related global
@@ -26,7 +26,7 @@ namespace llvm {
 
 class Record;
 class RecordKeeper;
-class CodeGenRegister;
+struct CodeGenRegister;
 
 /// getValueType - Return the MVT::ValueType that the specified TableGen record
 /// corresponds to.
@@ -46,8 +46,12 @@ class CodeGenTarget {
 
   mutable std::map<std::string, CodeGenInstruction> Instructions;
   mutable std::vector<CodeGenRegister> Registers;
-  void ReadInstructions() const;
+  mutable std::vector<CodeGenRegisterClass> RegisterClasses;
+  mutable std::vector<MVT::ValueType> LegalValueTypes;
   void ReadRegisters() const;
+  void ReadRegisterClasses() const;
+  void ReadInstructions() const;
+  void ReadLegalValueTypes() const;
 public:
   CodeGenTarget();
 
@@ -68,11 +72,30 @@ public:
   ///
   Record *getAsmWriter() const;
 
-  const std::vector<CodeGenRegister> &getRegisters() {
+  const std::vector<CodeGenRegister> &getRegisters() const {
     if (Registers.empty()) ReadRegisters();
     return Registers;
   }
 
+  const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
+    if (RegisterClasses.empty()) ReadRegisterClasses();
+    return RegisterClasses;
+  }
+
+  const std::vector<MVT::ValueType> &getLegalValueTypes() const {
+    if (LegalValueTypes.empty()) ReadLegalValueTypes();
+    return LegalValueTypes;
+  }
+  
+  /// isLegalValueType - Return true if the specified value type is natively
+  /// supported by the target (i.e. there are registers that directly hold it).
+  bool isLegalValueType(MVT::ValueType VT) const {
+    const std::vector<MVT::ValueType> &LegalVTs = getLegalValueTypes();
+    for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
+      if (LegalVTs[i] == VT) return true;
+    return false;    
+  }
+
   /// getInstructions - Return all of the instructions defined for this target.
   ///
   const std::map<std::string, CodeGenInstruction> &getInstructions() const {
@@ -80,14 +103,30 @@ public:
     return Instructions;
   }
 
+  CodeGenInstruction &getInstruction(const std::string &Name) const {
+    const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
+    assert(Insts.count(Name) && "Not an instruction!");
+    return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
+  }
+
   typedef std::map<std::string,
                    CodeGenInstruction>::const_iterator inst_iterator;
   inst_iterator inst_begin() const { return getInstructions().begin(); }
   inst_iterator inst_end() const { return Instructions.end(); }
 
+  /// getInstructionsByEnumValue - Return all of the instructions defined by the
+  /// target, ordered by their enum value.
+  void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
+                                                &NumberedInstructions);
+
+
   /// getPHIInstruction - Return the designated PHI instruction.
   ///
   const CodeGenInstruction &getPHIInstruction() const;
+
+  /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
+  ///
+  bool isLittleEndianEncoding() const;
 };
 
 } // End llvm namespace