Implement the last major missing piece in the DAG isel generator: when emitting

[oota-llvm.git] / utils / TableGen / CodeGenTarget.h

diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index c50d0576e80647b16b8bbbdbbade590fb97eac83..aaa6c7a426f5e0ac53b7def161cba1b852f6bdfb 100644 (file)
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -1,27 +1,40 @@
-//===- CodeGenWrappers.h - Code Generation Class Wrappers -------*- C++ -*-===//
+//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
 //
-// These classes wrap target description classes used by the various code
-// generation TableGen backends.  This makes it easier to access the data and
-// provides a single place that needs to check it for validity.  All of these
-// classes throw exceptions on error conditions.
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines wrappers for the Target class and related global
+// functionality.  This makes it easier to access the data and provides a single
+// place that needs to check it for validity.  All of these classes throw
+// exceptions on error conditions.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef CODEGENWRAPPERS_H
-#define CODEGENWRAPPERS_H
+#ifndef CODEGEN_TARGET_H
+#define CODEGEN_TARGET_H
 
-#include "llvm/CodeGen/ValueTypes.h"
+#include "CodeGenRegisters.h"
+#include "CodeGenInstruction.h"
 #include <iosfwd>
-#include <vector>
+#include <map>
+
+namespace llvm {
+
 class Record;
 class RecordKeeper;
+struct CodeGenRegister;
 
 /// getValueType - Return the MVT::ValueType that the specified TableGen record
 /// corresponds to.
 MVT::ValueType getValueType(Record *Rec);
 
 std::ostream &operator<<(std::ostream &OS, MVT::ValueType T);
-
+std::string getName(MVT::ValueType T);
+std::string getEnumName(MVT::ValueType T);
 
 
 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
@@ -31,6 +44,14 @@ class CodeGenTarget {
   std::vector<Record*> CalleeSavedRegisters;
   MVT::ValueType PointerType;
 
+  mutable std::map<std::string, CodeGenInstruction> Instructions;
+  mutable std::vector<CodeGenRegister> Registers;
+  mutable std::vector<CodeGenRegisterClass> RegisterClasses;
+  mutable std::vector<MVT::ValueType> LegalValueTypes;
+  void ReadRegisters() const;
+  void ReadRegisterClasses() const;
+  void ReadInstructions() const;
+  void ReadLegalValueTypes() const;
 public:
   CodeGenTarget();
 
@@ -41,12 +62,73 @@ public:
     return CalleeSavedRegisters;
   }
 
-  // getInstructionSet - Return the InstructionSet object...
+  MVT::ValueType getPointerType() const { return PointerType; }
+
+  /// getInstructionSet - Return the InstructionSet object.
+  ///
   Record *getInstructionSet() const;
 
-  // getInstructionSet - Return the CodeGenInstructionSet object for this
-  // target, lazily reading it from the record keeper as needed.
-  // CodeGenInstructionSet *getInstructionSet -
+  /// getAsmWriter - Return the AssemblyWriter definition for this target.
+  ///
+  Record *getAsmWriter() const;
+
+  const std::vector<CodeGenRegister> &getRegisters() const {
+    if (Registers.empty()) ReadRegisters();
+    return Registers;
+  }
+
+  const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
+    if (RegisterClasses.empty()) ReadRegisterClasses();
+    return RegisterClasses;
+  }
+
+  const std::vector<MVT::ValueType> &getLegalValueTypes() const {
+    if (LegalValueTypes.empty()) ReadLegalValueTypes();
+    return LegalValueTypes;
+  }
+  
+  /// isLegalValueType - Return true if the specified value type is natively
+  /// supported by the target (i.e. there are registers that directly hold it).
+  bool isLegalValueType(MVT::ValueType VT) const {
+    const std::vector<MVT::ValueType> &LegalVTs = getLegalValueTypes();
+    for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
+      if (LegalVTs[i] == VT) return true;
+    return false;    
+  }
+
+  /// getInstructions - Return all of the instructions defined for this target.
+  ///
+  const std::map<std::string, CodeGenInstruction> &getInstructions() const {
+    if (Instructions.empty()) ReadInstructions();
+    return Instructions;
+  }
+
+  CodeGenInstruction &getInstruction(const std::string &Name) const {
+    const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
+    assert(Insts.count(Name) && "Not an instruction!");
+    return const_cast<CodeGenInstruction&>(Insts.find(Name)->second);
+  }
+
+  typedef std::map<std::string,
+                   CodeGenInstruction>::const_iterator inst_iterator;
+  inst_iterator inst_begin() const { return getInstructions().begin(); }
+  inst_iterator inst_end() const { return Instructions.end(); }
+
+  /// getInstructionsByEnumValue - Return all of the instructions defined by the
+  /// target, ordered by their enum value.
+  void getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
+                                                &NumberedInstructions);
+
+
+  /// getPHIInstruction - Return the designated PHI instruction.
+  ///
+  const CodeGenInstruction &getPHIInstruction() const;
+
+  /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
+  ///
+  bool isLittleEndianEncoding() const;
 };
 
+} // End llvm namespace
+
 #endif