Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step

[oota-llvm.git] / utils / TableGen / DisassemblerEmitter.cpp

diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp
index e68592d007972b06c614104d057fb90ee315f785..2d8bf6634aa8fb345dc30f562f70ab08504a4c20 100644 (file)
--- a/utils/TableGen/DisassemblerEmitter.cpp
+++ b/utils/TableGen/DisassemblerEmitter.cpp
@@ -12,7 +12,7 @@
 #include "Record.h"
 #include "X86DisassemblerTables.h"
 #include "X86RecognizableInstr.h"
-#include "RISCDisassemblerEmitter.h"
+#include "ARMDecoderEmitter.h"
 
 using namespace llvm;
 using namespace llvm::X86Disassembler;
@@ -94,7 +94,7 @@ using namespace llvm::X86Disassembler;
 ///   instruction.
 
 void DisassemblerEmitter::run(raw_ostream &OS) {
-  CodeGenTarget Target;
+  CodeGenTarget Target(Records);
 
   OS << "/*===- TableGen'erated file "
      << "---------------------------------------*- C -*-===*\n"
@@ -110,8 +110,8 @@ void DisassemblerEmitter::run(raw_ostream &OS) {
   if (Target.getName() == "X86") {
     DisassemblerTables Tables;
   
-    std::vector<const CodeGenInstruction*> numberedInstructions;
-    Target.getInstructionsByEnumValue(numberedInstructions);
+    const std::vector<const CodeGenInstruction*> &numberedInstructions =
+      Target.getInstructionsByEnumValue();
     
     for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
       RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
@@ -128,7 +128,7 @@ void DisassemblerEmitter::run(raw_ostream &OS) {
 
   // Fixed-instruction-length targets use a common disassembler.
   if (Target.getName() == "ARM") {
-    RISCDisassemblerEmitter(Records).run(OS);
+    ARMDecoderEmitter(Records).run(OS);
     return;
   }