Teach the clang attribute emitter about InheritableParamAttr.

[oota-llvm.git] / utils / TableGen / DisassemblerEmitter.cpp

diff --git a/utils/TableGen/DisassemblerEmitter.cpp b/utils/TableGen/DisassemblerEmitter.cpp
index 61b9b1583b250aeb026e796b23a57dd3ed75141d..90a2af21f3a4a5f15ad148a169eb5459c5fe0caa 100644 (file)
--- a/utils/TableGen/DisassemblerEmitter.cpp
+++ b/utils/TableGen/DisassemblerEmitter.cpp
@@ -12,6 +12,9 @@
 #include "Record.h"
 #include "X86DisassemblerTables.h"
 #include "X86RecognizableInstr.h"
+#include "ARMDecoderEmitter.h"
+#include "FixedLenDecoderEmitter.h"
+
 using namespace llvm;
 using namespace llvm::X86Disassembler;
 
@@ -92,7 +95,7 @@ using namespace llvm::X86Disassembler;
 ///   instruction.
 
 void DisassemblerEmitter::run(raw_ostream &OS) {
-  CodeGenTarget Target;
+  CodeGenTarget Target(Records);
 
   OS << "/*===- TableGen'erated file "
      << "---------------------------------------*- C -*-===*\n"
@@ -108,8 +111,8 @@ void DisassemblerEmitter::run(raw_ostream &OS) {
   if (Target.getName() == "X86") {
     DisassemblerTables Tables;
   
-    std::vector<const CodeGenInstruction*> numberedInstructions;
-    Target.getInstructionsByEnumValue(numberedInstructions);
+    const std::vector<const CodeGenInstruction*> &numberedInstructions =
+      Target.getInstructionsByEnumValue();
     
     for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
       RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
@@ -124,6 +127,12 @@ void DisassemblerEmitter::run(raw_ostream &OS) {
     return;
   }
 
-  throw TGError(Target.getTargetRecord()->getLoc(),
-                "Unable to generate disassembler for this target");
+  // Fixed-instruction-length targets use a common disassembler.
+  // ARM use its own implementation for now.
+  if (Target.getName() == "ARM") {
+    ARMDecoderEmitter(Records).run(OS);
+    return;
+  }  
+
+  FixedLenDecoderEmitter(Records).run(OS);
 }