///
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
- MVT::SimpleValueType VT,
- const CodeGenRegisterClass *DstRC) {
+ MVT::SimpleValueType VT) {
+ if (!InstPatNode->isLeaf() &&
+ InstPatNode->getOperator()->getName() == "imm") {
+ Operands.push_back("i");
+ return true;
+ }
+ if (!InstPatNode->isLeaf() &&
+ InstPatNode->getOperator()->getName() == "fpimm") {
+ Operands.push_back("f");
+ return true;
+ }
+
+ const CodeGenRegisterClass *DstRC = 0;
+
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
// For now, filter out any operand with a predicate.
Operands.push_back("i");
return true;
}
- // For now, ignore fpimm and other non-leaf nodes.
+ if (Op->getOperator()->getName() == "fpimm") {
+ Operands.push_back("f");
+ return true;
+ }
+ // For now, ignore other non-leaf nodes.
return false;
}
DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
if (!RC)
return false;
// For now, all the operands must have the same register class.
- if (DstRC != RC)
- return false;
+ if (DstRC) {
+ if (DstRC != RC)
+ return false;
+ } else
+ DstRC = RC;
Operands.push_back("r");
}
return true;
OS << "unsigned Op" << i;
} else if (Operands[i] == "i") {
OS << "uint64_t imm" << i;
+ } else if (Operands[i] == "f") {
+ OS << "ConstantFP *f" << i;
} else {
assert("Unknown operand kind!");
abort();
OS << "Op" << i;
} else if (Operands[i] == "i") {
OS << "imm" << i;
+ } else if (Operands[i] == "f") {
+ OS << "f" << i;
} else {
assert("Unknown operand kind!");
abort();
struct InstructionMemo {
std::string Name;
const CodeGenRegisterClass *RC;
+ unsigned char SubRegNo;
+};
+
+class FastISelMap {
+ typedef std::map<std::string, InstructionMemo> PredMap;
+ typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
+ typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
+ typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
+ typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
+
+ OperandsOpcodeTypeRetPredMap SimplePatterns;
+
+ std::string InstNS;
+
+public:
+ explicit FastISelMap(std::string InstNS);
+
+ void CollectPatterns(CodeGenDAGPatterns &CGP);
+ void PrintClass(std::ostream &OS);
+ void PrintFunctionDefinitions(std::ostream &OS);
};
}
return OpName;
}
-void FastISelEmitter::run(std::ostream &OS) {
- EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
- Target.getName() + " target", OS);
+FastISelMap::FastISelMap(std::string instns)
+ : InstNS(instns) {
+}
- OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
- OS << "\n";
- OS << "namespace llvm {\n";
- OS << "\n";
- OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
- OS << "\n";
-
- typedef std::map<std::string, InstructionMemo> PredMap;
- typedef std::map<MVT::SimpleValueType, PredMap> TypePredMap;
- typedef std::map<std::string, TypePredMap> OpcodeTypePredMap;
- typedef std::map<OperandsSignature, OpcodeTypePredMap> OperandsOpcodeTypePredMap;
- OperandsOpcodeTypePredMap SimplePatterns;
+void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
+ const CodeGenTarget &Target = CGP.getTargetInfo();
+
+ // Determine the target's namespace name.
+ InstNS = Target.getInstNamespace() + "::";
+ assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
// Scan through all the patterns and record the simple ones.
for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
// For now, ignore instructions where the first operand is not an
// output register.
- Record *Op0Rec = II.OperandList[0].Rec;
- if (!Op0Rec->isSubClassOf("RegisterClass"))
- continue;
- const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
- if (!DstRC)
- continue;
+ const CodeGenRegisterClass *DstRC = 0;
+ unsigned SubRegNo = ~0;
+ if (Op->getName() != "EXTRACT_SUBREG") {
+ Record *Op0Rec = II.OperandList[0].Rec;
+ if (!Op0Rec->isSubClassOf("RegisterClass"))
+ continue;
+ DstRC = &Target.getRegisterClass(Op0Rec);
+ if (!DstRC)
+ continue;
+ } else {
+ SubRegNo = static_cast<IntInit*>(
+ Dst->getChild(1)->getLeafValue())->getValue();
+ }
// Inspect the pattern.
TreePatternNode *InstPatNode = Pattern.getSrcPattern();
Record *InstPatOp = InstPatNode->getOperator();
std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
- MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
+ MVT::SimpleValueType VT = RetVT;
+ if (InstPatNode->getNumChildren())
+ VT = InstPatNode->getChild(0)->getTypeNum(0);
// For now, filter out instructions which just set a register to
// an Operand or an immediate, like MOV32ri.
if (InstPatOp->isSubClassOf("Operand"))
continue;
- if (InstPatOp->getName() == "imm" ||
- InstPatOp->getName() == "fpimm")
- continue;
// For now, filter out any instructions with predicates.
if (!InstPatNode->getPredicateFn().empty())
// Check all the operands.
OperandsSignature Operands;
- if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
+ if (!Operands.initialize(InstPatNode, Target, VT))
continue;
// Get the predicate that guards this pattern.
// Ok, we found a pattern that we can handle. Remember it.
InstructionMemo Memo = {
Pattern.getDstPattern()->getOperator()->getName(),
- DstRC
+ DstRC,
+ SubRegNo
};
- assert(!SimplePatterns[Operands][OpcodeName][VT].count(PredicateCheck) &&
+ assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
"Duplicate pattern!");
- SimplePatterns[Operands][OpcodeName][VT][PredicateCheck] = Memo;
+ SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
}
+}
+void FastISelMap::PrintClass(std::ostream &OS) {
// Declare the target FastISel class.
OS << "class FastISel : public llvm::FastISel {\n";
- for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
+ for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
OE = SimplePatterns.end(); OI != OE; ++OI) {
const OperandsSignature &Operands = OI->first;
- const OpcodeTypePredMap &OTM = OI->second;
+ const OpcodeTypeRetPredMap &OTM = OI->second;
- for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+ for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
const std::string &Opcode = I->first;
- const TypePredMap &TM = I->second;
+ const TypeRetPredMap &TM = I->second;
- for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+ for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
-
+ const RetPredMap &RM = TI->second;
+
+ if (RM.size() != 1)
+ for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+ RI != RE; ++RI) {
+ MVT::SimpleValueType RetVT = RI->first;
+ OS << " unsigned FastEmit_" << getLegalCName(Opcode)
+ << "_" << getLegalCName(getName(VT)) << "_"
+ << getLegalCName(getName(RetVT)) << "_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(";
+ Operands.PrintParameters(OS);
+ OS << ");\n";
+ }
+
OS << " unsigned FastEmit_" << getLegalCName(Opcode)
<< "_" << getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(";
+ OS << "(MVT::SimpleValueType RetVT";
+ if (!Operands.empty())
+ OS << ", ";
Operands.PrintParameters(OS);
OS << ");\n";
}
OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT";
+ OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << " unsigned FastEmit_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+ OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
<< "Subtarget>()) {}\n";
OS << "};\n";
OS << "\n";
+}
- // Define the target FastISel creation function.
- OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
- OS << " return new FastISel(mf);\n";
- OS << "}\n";
- OS << "\n";
-
+void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
// Now emit code for all the patterns that we collected.
- for (OperandsOpcodeTypePredMap::const_iterator OI = SimplePatterns.begin(),
+ for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
OE = SimplePatterns.end(); OI != OE; ++OI) {
const OperandsSignature &Operands = OI->first;
- const OpcodeTypePredMap &OTM = OI->second;
+ const OpcodeTypeRetPredMap &OTM = OI->second;
- for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+ for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
const std::string &Opcode = I->first;
- const TypePredMap &TM = I->second;
+ const TypeRetPredMap &TM = I->second;
OS << "// FastEmit functions for " << Opcode << ".\n";
OS << "\n";
// Emit one function for each opcode,type pair.
- for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+ for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
- const PredMap &PM = TI->second;
- bool HasPred = false;
-
- OS << "unsigned FastISel::FastEmit_"
- << getLegalCName(Opcode)
- << "_" << getLegalCName(getName(VT)) << "_";
- Operands.PrintManglingSuffix(OS);
- OS << "(";
- Operands.PrintParameters(OS);
- OS << ") {\n";
-
- // Emit code for each possible instruction. There may be
- // multiple if there are subtarget concerns.
- for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
- PI != PE; ++PI) {
- std::string PredicateCheck = PI->first;
- const InstructionMemo &Memo = PI->second;
+ const RetPredMap &RM = TI->second;
+ if (RM.size() != 1) {
+ for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+ RI != RE; ++RI) {
+ MVT::SimpleValueType RetVT = RI->first;
+ const PredMap &PM = RI->second;
+ bool HasPred = false;
+
+ OS << "unsigned FastISel::FastEmit_"
+ << getLegalCName(Opcode)
+ << "_" << getLegalCName(getName(VT))
+ << "_" << getLegalCName(getName(RetVT)) << "_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(";
+ Operands.PrintParameters(OS);
+ OS << ") {\n";
+
+ // Emit code for each possible instruction. There may be
+ // multiple if there are subtarget concerns.
+ for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
+ PI != PE; ++PI) {
+ std::string PredicateCheck = PI->first;
+ const InstructionMemo &Memo = PI->second;
- if (PredicateCheck.empty()) {
- assert(!HasPred && "Multiple instructions match, at least one has "
- "a predicate and at least one doesn't!");
- } else {
- OS << " if (" + PredicateCheck + ")\n";
- OS << " ";
- HasPred = true;
+ if (PredicateCheck.empty()) {
+ assert(!HasPred &&
+ "Multiple instructions match, at least one has "
+ "a predicate and at least one doesn't!");
+ } else {
+ OS << " if (" + PredicateCheck + ")\n";
+ OS << " ";
+ HasPred = true;
+ }
+ OS << " return FastEmitInst_";
+ if (Memo.SubRegNo == (unsigned char)~0) {
+ Operands.PrintManglingSuffix(OS);
+ OS << "(" << InstNS << Memo.Name << ", ";
+ OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ } else {
+ OS << "extractsubreg(Op0, ";
+ OS << (unsigned)Memo.SubRegNo;
+ OS << ");\n";
+ }
+ }
+ // Return 0 if none of the predicates were satisfied.
+ if (HasPred)
+ OS << " return 0;\n";
+ OS << "}\n";
+ OS << "\n";
}
- OS << " return FastEmitInst_";
+
+ // Emit one function for the type that demultiplexes on return type.
+ OS << "unsigned FastISel::FastEmit_"
+ << getLegalCName(Opcode) << "_"
+ << getLegalCName(getName(VT)) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(" << InstNS << Memo.Name << ", ";
- OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ OS << "(MVT::SimpleValueType RetVT";
if (!Operands.empty())
OS << ", ";
- Operands.PrintArguments(OS);
- OS << ");\n";
+ Operands.PrintParameters(OS);
+ OS << ") {\nswitch (RetVT) {\n";
+ for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
+ RI != RE; ++RI) {
+ MVT::SimpleValueType RetVT = RI->first;
+ OS << " case " << getName(RetVT) << ": return FastEmit_"
+ << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
+ << "_" << getLegalCName(getName(RetVT)) << "_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ }
+ OS << " default: return 0;\n}\n}\n\n";
+
+ } else {
+ // Non-variadic return type.
+ OS << "unsigned FastISel::FastEmit_"
+ << getLegalCName(Opcode) << "_"
+ << getLegalCName(getName(VT)) << "_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(MVT::SimpleValueType RetVT";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintParameters(OS);
+ OS << ") {\n";
+
+ OS << " if (RetVT != " << getName(RM.begin()->first)
+ << ")\n return 0;\n";
+
+ const PredMap &PM = RM.begin()->second;
+ bool HasPred = false;
+
+ // Emit code for each possible instruction. There may be
+ // multiple if there are subtarget concerns.
+ for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) {
+ std::string PredicateCheck = PI->first;
+ const InstructionMemo &Memo = PI->second;
+
+ if (PredicateCheck.empty()) {
+ assert(!HasPred &&
+ "Multiple instructions match, at least one has "
+ "a predicate and at least one doesn't!");
+ } else {
+ OS << " if (" + PredicateCheck + ")\n";
+ OS << " ";
+ HasPred = true;
+ }
+ OS << " return FastEmitInst_";
+
+ if (Memo.SubRegNo == (unsigned char)~0) {
+ Operands.PrintManglingSuffix(OS);
+ OS << "(" << InstNS << Memo.Name << ", ";
+ OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ } else {
+ OS << "extractsubreg(Op0, ";
+ OS << (unsigned)Memo.SubRegNo;
+ OS << ");\n";
+ }
+ }
+
+ // Return 0 if none of the predicates were satisfied.
+ if (HasPred)
+ OS << " return 0;\n";
+ OS << "}\n";
+ OS << "\n";
}
- // Return 0 if none of the predicates were satisfied.
- if (HasPred)
- OS << " return 0;\n";
- OS << "}\n";
- OS << "\n";
}
// Emit one function for the opcode that demultiplexes based on the type.
OS << "unsigned FastISel::FastEmit_"
<< getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT";
+ OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
OS << " switch (VT) {\n";
- for (TypePredMap::const_iterator TI = TM.begin(), TE = TM.end();
+ for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
TI != TE; ++TI) {
MVT::SimpleValueType VT = TI->first;
std::string TypeName = getName(VT);
OS << " case " << TypeName << ": return FastEmit_"
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(";
+ OS << "(RetVT";
+ if (!Operands.empty())
+ OS << ", ";
Operands.PrintArguments(OS);
OS << ");\n";
}
// on opcode and type.
OS << "unsigned FastISel::FastEmit_";
Operands.PrintManglingSuffix(OS);
- OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+ OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
if (!Operands.empty())
OS << ", ";
Operands.PrintParameters(OS);
OS << ") {\n";
OS << " switch (Opcode) {\n";
- for (OpcodeTypePredMap::const_iterator I = OTM.begin(), E = OTM.end();
+ for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
I != E; ++I) {
const std::string &Opcode = I->first;
OS << " case " << Opcode << ": return FastEmit_"
<< getLegalCName(Opcode) << "_";
Operands.PrintManglingSuffix(OS);
- OS << "(VT";
+ OS << "(VT, RetVT";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS);
OS << "}\n";
OS << "\n";
}
+}
+
+void FastISelEmitter::run(std::ostream &OS) {
+ const CodeGenTarget &Target = CGP.getTargetInfo();
+
+ // Determine the target's namespace name.
+ std::string InstNS = Target.getInstNamespace() + "::";
+ assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
+
+ EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
+ Target.getName() + " target", OS);
+
+ OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
+ OS << "\n";
+ OS << "namespace llvm {\n";
+ OS << "\n";
+ OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n";
+ OS << "\n";
+
+ FastISelMap F(InstNS);
+ F.CollectPatterns(CGP);
+ F.PrintClass(OS);
+ F.PrintFunctionDefinitions(OS);
+
+ // Define the target FastISel creation function.
+ OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n";
+ OS << " return new FastISel(mf);\n";
+ OS << "}\n";
+ OS << "\n";
OS << "} // namespace X86\n";
OS << "\n";
FastISelEmitter::FastISelEmitter(RecordKeeper &R)
: Records(R),
- CGP(R),
- Target(CGP.getTargetInfo()),
- InstNS(Target.getInstNamespace() + "::") {
-
- assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
+ CGP(R) {
}
+
projects / oota-llvm.git / blobdiff