//
//===----------------------------------------------------------------------===//
//
-// This tablegen backend emits a "fast" instruction selector.
+// This tablegen backend emits code for use by the "fast" instruction
+// selection algorithm. See the comments at the top of
+// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
//
-// This instruction selection method is designed to emit very poor code
-// quickly. Also, it is not designed to do much lowering, so most illegal
-// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
-// supported and cannot easily be added. Blocks containing operations
-// that are not supported need to be handled by a more capable selector,
-// such as the SelectionDAG selector.
+// This file scans through the target's tablegen instruction-info files
+// and extracts instructions with obvious-looking patterns, and it emits
+// code to look up these instructions by type and operator.
//
-// The intended use for "fast" instruction selection is "-O0" mode
-// compilation, where the quality of the generated code is irrelevant when
-// weighed against the speed at which the code can be generated.
-//
-// If compile time is so important, you might wonder why we don't just
-// skip codegen all-together, emit LLVM bytecode files, and execute them
-// with an interpreter. The answer is that it would complicate linking and
-// debugging, and also because that isn't how a compiler is expected to
-// work in some circles.
-//
-// If you need better generated code or more lowering than what this
-// instruction selector provides, use the SelectionDAG (DAGISel) instruction
-// selector instead. If you're looking here because SelectionDAG isn't fast
-// enough, consider looking into improving the SelectionDAG infastructure
-// instead. At the time of this writing there remain several major
-// opportunities for improvement.
-//
//===----------------------------------------------------------------------===//
#include "FastISelEmitter.h"
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
// For now, filter out any operand with a predicate.
- if (!Op->getPredicateFn().empty())
+ if (!Op->getPredicateFns().empty())
return false;
// For now, filter out any operand with multiple values.
if (Op->getExtTypes().size() != 1)
return false;
Record *OpLeafRec = OpDI->getDef();
// For now, the only other thing we accept is register operands.
-
+
const CodeGenRegisterClass *RC = 0;
if (OpLeafRec->isSubClassOf("RegisterClass"))
RC = &Target.getRegisterClass(OpLeafRec);
void PrintArguments(std::ostream &OS,
const std::vector<std::string>& PR) const {
assert(PR.size() == Operands.size());
+ bool PrintedArg = false;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
- if (PR[i] != "") {
- OS << PR[i];
- } else if (Operands[i] == "r") {
+ if (PR[i] != "")
+ // Implicit physical register operand.
+ continue;
+
+ if (PrintedArg)
+ OS << ", ";
+ if (Operands[i] == "r") {
OS << "Op" << i;
+ PrintedArg = true;
} else if (Operands[i] == "i") {
OS << "imm" << i;
+ PrintedArg = true;
} else if (Operands[i] == "f") {
OS << "f" << i;
+ PrintedArg = true;
} else {
assert("Unknown operand kind!");
abort();
}
- if (i + 1 != e)
- OS << ", ";
}
}
}
+ void PrintManglingSuffix(std::ostream &OS,
+ const std::vector<std::string>& PR) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (PR[i] != "")
+ // Implicit physical register operand. e.g. Instruction::Mul expect to
+ // select to a binary op. On x86, mul may take a single operand with
+ // the other operand being implicit. We must emit something that looks
+ // like a binary instruction except for the very inner FastEmitInst_*
+ // call.
+ continue;
+ OS << Operands[i];
+ }
+ }
+
void PrintManglingSuffix(std::ostream &OS) const {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
OS << Operands[i];
continue;
// For now, filter out any instructions with predicates.
- if (!InstPatNode->getPredicateFn().empty())
+ if (!InstPatNode->getPredicateFns().empty())
continue;
// Check all the operands.
OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
- Operands.PrintManglingSuffix(OS);
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
}
if (HasPred)
- OS << "}\n";
+ OS << " }\n";
}
// Return 0 if none of the predicates were satisfied.
// Emit code for each possible instruction. There may be
// multiple if there are subtarget concerns.
- for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) {
+ for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
+ ++PI) {
std::string PredicateCheck = PI->first;
const InstructionMemo &Memo = PI->second;
OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
- Operands.PrintManglingSuffix(OS);
+ Operands.PrintManglingSuffix(OS, *Memo.PhysRegs);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
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