Generalize the register matching code in DAGISel a bit.

[oota-llvm.git] / utils / TableGen / InstrEnumEmitter.cpp

diff --git a/utils/TableGen/InstrEnumEmitter.cpp b/utils/TableGen/InstrEnumEmitter.cpp
index df07119944e4c5979b9176277eec23b516b54906..aa596892f52f0916b45efc46086de6c079e2001d 100644 (file)
--- a/utils/TableGen/InstrEnumEmitter.cpp
+++ b/utils/TableGen/InstrEnumEmitter.cpp
@@ -15,32 +15,26 @@
 #include "InstrEnumEmitter.h"
 #include "CodeGenTarget.h"
 #include "Record.h"
+#include <cstdio>
 using namespace llvm;
 
 // runEnums - Print out enum values for all of the instructions.
-void InstrEnumEmitter::run(std::ostream &OS) {
+void InstrEnumEmitter::run(raw_ostream &OS) {
   EmitSourceFileHeader("Target Instruction Enum Values", OS);
   OS << "namespace llvm {\n\n";
 
-  CodeGenTarget Target;
+  CodeGenTarget Target(Records);
 
   // We must emit the PHI opcode first...
-  std::string Namespace;
-  for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 
-       E = Target.inst_end(); II != E; ++II) {
-    if (II->second.Namespace != "TargetInstrInfo") {
-      Namespace = II->second.Namespace;
-      break;
-    }
-  }
+  std::string Namespace = Target.getInstNamespace();
   
   if (Namespace.empty()) {
     fprintf(stderr, "No instructions defined!\n");
     exit(1);
   }
 
-  std::vector<const CodeGenInstruction*> NumberedInstructions;
-  Target.getInstructionsByEnumValue(NumberedInstructions);
+  const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+    Target.getInstructionsByEnumValue();
 
   OS << "namespace " << Namespace << " {\n";
   OS << "  enum {\n";