#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "Record.h"
+#include <algorithm>
using namespace llvm;
// runEnums - Print out enum values for all of the instructions.
CodeGenTarget Target;
// We must emit the PHI opcode first...
- Record *InstrInfo = Target.getInstructionSet();
-
- std::string Namespace = Target.inst_begin()->second.Namespace;
-
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << " enum {\n";
+ std::string Namespace;
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+ if (II->second.Namespace != "TargetInstrInfo") {
+ Namespace = II->second.Namespace;
+ break;
+ }
+ }
+
+ if (Namespace.empty()) {
+ std::cerr << "No instructions defined!\n";
+ exit(1);
+ }
std::vector<const CodeGenInstruction*> NumberedInstructions;
Target.getInstructionsByEnumValue(NumberedInstructions);
+ OS << "namespace " << Namespace << " {\n";
+ OS << " enum {\n";
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
OS << " " << NumberedInstructions[i]->TheDef->getName()
- << ", \t// " << i << "\n";
+ << "\t= " << i << ",\n";
}
- OS << " INSTRUCTION_LIST_END\n";
- OS << " };\n";
- if (!Namespace.empty())
- OS << "}\n";
+ OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+ OS << " };\n}\n";
OS << "} // End llvm namespace \n";
}
OS << "0 };\n";
}
-static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
- std::vector<Record*> Result;
- if (Inst.hasVariableNumberOfOperands)
- return Result; // No info for variable operand instrs.
-
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+ std::vector<std::string> Result;
for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
- if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
- Result.push_back(Inst.OperandList[i].Rec);
- else {
- // This might be a multiple operand thing.
- // FIXME: Targets like X86 have registers in their multi-operand operands.
- for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
- Result.push_back(0);
+ if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
+ std::string OpStr = getQualifiedName(Inst.OperandList[i].Rec);
+ OpStr += "RegClassID, 0, ";
+ OpStr += Inst.OperandList[i].Constraint;
+
+ Result.push_back(OpStr);
+ } else {
+ // This might be a multiple operand thing. Targets like X86 have
+ // registers in their multi-operand operands. It may also be an anonymous
+ // operand, which has a single operand, but no declared class for the
+ // operand.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+
+ for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
+ Record *OpR = 0;
+ if (MIOI && j < MIOI->getNumArgs())
+ if (DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j)))
+ OpR = Def->getDef();
+
+
+ std::string Res;
+
+ if (OpR && OpR->isSubClassOf("RegisterClass"))
+ Res += getQualifiedName(OpR) + "RegClassID, ";
+ else
+ Res += "0, ";
+
+ // Fill in applicable flags.
+ Res += "0";
+
+ // Ptr value whose register class is resolved via callback.
+ if (OpR && OpR->getName() == "ptr_rc")
+ Res += "|M_LOOK_UP_PTR_REG_CLASS";
+
+ // Predicate operands.
+ if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+ Res += "|M_PREDICATE_OPERAND";
+
+ // fill in constraint info.
+ Res += ", " + Inst.OperandList[i].Constraint;
+
+ Result.push_back(Res);
+ }
}
}
+
return Result;
}
// run - Emit the main instruction description records for the target...
void InstrInfoEmitter::run(std::ostream &OS) {
+ GatherItinClasses();
+
EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
CodeGenTarget Target;
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
- Record *PHI = InstrInfo->getValueAsDef("PHIInst");
-
- // Emit empty implicit uses and defs lists
- OS << "static const unsigned EmptyImpList[] = { 0 };\n";
// Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists;
}
}
- std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
+ std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
unsigned OperandListNum = 0;
- OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+ OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
// Emit all of the operand info records.
OS << "\n";
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
+ std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
unsigned &N = OperandInfosEmitted[OperandInfo];
if (N == 0) {
N = ++OperandListNum;
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
- for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
- if (Record *RC = OperandInfo[i]) {
- OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
- } else {
- OS << "{ 0 }, ";
- }
- }
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
OS << "};\n";
}
}
- // Emit all of the TargetInstrDescriptor records.
+ // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
//
OS << "\nstatic const TargetInstrDescriptor " << TargetName
<< "Insts[] = {\n";
- emitRecord(Target.getPHIInstruction(), 0, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
+ std::vector<const CodeGenInstruction*> NumberedInstructions;
+ Target.getInstructionsByEnumValue(NumberedInstructions);
- unsigned i = 0;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II)
- if (II->second.TheDef != PHI)
- emitRecord(II->second, ++i, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
+ emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
+ OperandInfosEmitted, OS);
OS << "};\n";
OS << "} // End llvm namespace \n";
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EmittedLists,
- std::map<std::vector<Record*>, unsigned> &OpInfo,
+ std::map<std::vector<std::string>, unsigned> &OpInfo,
std::ostream &OS) {
- int NumOperands;
- if (Inst.hasVariableNumberOfOperands)
- NumOperands = -1;
- else if (!Inst.OperandList.empty())
+ int MinOperands;
+ if (!Inst.OperandList.empty())
// Each logical operand can be multiple MI operands.
- NumOperands = Inst.OperandList.back().MIOperandNo +
+ MinOperands = Inst.OperandList.back().MIOperandNo +
Inst.OperandList.back().MINumOperands;
else
- NumOperands = 0;
+ MinOperands = 0;
OS << " { \"";
if (Inst.Name.empty())
OS << Inst.TheDef->getName();
else
OS << Inst.Name;
- OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
+
+ unsigned ItinClass = !IsItineraries ? 0 :
+ ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
+
+ OS << "\",\t" << MinOperands << ", " << ItinClass
+ << ", 0";
+
+ // Try to determine (from the pattern), if the instruction is a store.
+ bool isStore = false;
+ if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
+ ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
+ if (LI && LI->getSize() > 0) {
+ DagInit *Dag = (DagInit *)LI->getElement(0);
+ DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
+ if (OpDef) {
+ Record *Operator = OpDef->getDef();
+ if (Operator->isSubClassOf("SDNode")) {
+ const std::string Opcode = Operator->getValueAsString("Opcode");
+ if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
+ isStore = true;
+ }
+ }
+ }
+ }
// Emit all of the target indepedent flags...
if (Inst.isReturn) OS << "|M_RET_FLAG";
if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
if (Inst.isCall) OS << "|M_CALL_FLAG";
if (Inst.isLoad) OS << "|M_LOAD_FLAG";
- if (Inst.isStore) OS << "|M_STORE_FLAG";
+ if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
+ if (Inst.isPredicated) OS << "|M_PREDICATED";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
+ if (Inst.hasVariableNumberOfOperands)
+ OS << "|M_VARIABLE_OPS";
OS << ", 0";
// Emit all of the target-specific flags...
// Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
// Emit the operand info.
- std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+ std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
OS << "0";
else
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
+struct LessRecord {
+ bool operator()(const Record *Rec1, const Record *Rec2) const {
+ return Rec1->getName() < Rec2->getName();
+ }
+};
+void InstrInfoEmitter::GatherItinClasses() {
+ std::vector<Record*> DefList =
+ Records.getAllDerivedDefinitions("InstrItinClass");
+ IsItineraries = !DefList.empty();
+
+ if (!IsItineraries) return;
+
+ std::sort(DefList.begin(), DefList.end(), LessRecord());
+
+ for (unsigned i = 0, N = DefList.size(); i < N; i++) {
+ Record *Def = DefList[i];
+ ItinClassMap[Def->getName()] = i;
+ }
+}
+
+unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
+ return ItinClassMap[ItinName];
+}
+
void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
IntInit *ShiftInt, std::ostream &OS) {
if (Val == 0 || ShiftInt == 0)
RecordVal *RV = R->getValue(Val->getValue());
int Shift = ShiftInt->getValue();
- if (RV == 0 || RV->getValue() == 0)
- throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
+ if (RV == 0 || RV->getValue() == 0) {
+ // This isn't an error if this is a builtin instruction.
+ if (R->getName() != "PHI" && R->getName() != "INLINEASM")
+ throw R->getName() + " doesn't have a field named '" +
+ Val->getValue() + "'!";
+ return;
+ }
Init *Value = RV->getValue();
if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
Init *I = BI->convertInitializerTo(new IntRecTy());
if (I)
if (IntInit *II = dynamic_cast<IntInit*>(I)) {
- if (II->getValue())
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ if (II->getValue()) {
+ if (Shift)
+ OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ else
+ OS << "|" << II->getValue();
+ }
return;
}
} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
- if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ if (II->getValue()) {
+ if (Shift)
+ OS << "|(" << II->getValue() << "<<" << Shift << ")";
+ else
+ OS << II->getValue();
+ }
return;
}
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