Mark predicate operands as such in operand info.

[oota-llvm.git] / utils / TableGen / InstrInfoEmitter.cpp

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index f91babcf860bccc03baea8e0a5af9ee6acacc109..0c5c4552035954eb3113a09f1bdaf6b9fbe6cd2c 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -14,6 +14,7 @@
 
 #include "InstrInfoEmitter.h"
 #include "CodeGenTarget.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "Record.h"
 #include <algorithm>
 using namespace llvm;
@@ -62,26 +63,56 @@ void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
   OS << "0 };\n";
 }
 
-static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
-  std::vector<Record*> Result;
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+  std::vector<std::string> Result;
   for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
     if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
-      Result.push_back(Inst.OperandList[i].Rec);
+      std::string OpStr = getQualifiedName(Inst.OperandList[i].Rec);
+      OpStr += "RegClassID, 0, ";
+      OpStr += Inst.OperandList[i].Constraint;
+
+      Result.push_back(OpStr);
     } else {
-      // This might be a multiple operand thing.
-      // Targets like X86 have registers in their multi-operand operands.
+      // This might be a multiple operand thing.  Targets like X86 have
+      // registers in their multi-operand operands.  It may also be an anonymous
+      // operand, which has a single operand, but no declared class for the
+      // operand.
       DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
-      unsigned NumDefs = MIOI->getNumArgs();
+      
       for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
-        if (NumDefs <= j) {
-          Result.push_back(0);
-        } else {
-          DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
-          Result.push_back(Def ? Def->getDef() : 0);
-        }
+        Record *OpR = 0;
+        if (MIOI && j < MIOI->getNumArgs())
+          if (DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j)))
+            OpR = Def->getDef();
+
+        
+        std::string Res;
+
+        if (OpR && OpR->isSubClassOf("RegisterClass"))
+          Res += getQualifiedName(OpR) + "RegClassID, ";
+        else
+          Res += "0, ";
+
+        // Fill in applicable flags.
+        Res += "0";
+        
+        // Ptr value whose register class is resolved via callback.
+        if (OpR && OpR->getName() == "ptr_rc")
+          Res += "|M_LOOK_UP_PTR_REG_CLASS";
+
+        // Predicate operands.
+        if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+          Res += "|M_PREDICATE_OPERAND";
+        
+        // fill in constraint info.
+        Res += ", " + Inst.OperandList[i].Constraint;
+        
+        Result.push_back(Res);
       }
     }
   }
+
   return Result;
 }
 
@@ -97,9 +128,6 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
 
-  // Emit empty implicit uses and defs lists
-  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
-
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
@@ -120,30 +148,21 @@ void InstrInfoEmitter::run(std::ostream &OS) {
     }
   }
 
-  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
+  std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
   unsigned OperandListNum = 0;
-  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+  OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
   
   // Emit all of the operand info records.
   OS << "\n";
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
        E = Target.inst_end(); II != E; ++II) {
-    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
+    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
     unsigned &N = OperandInfosEmitted[OperandInfo];
     if (N == 0) {
       N = ++OperandListNum;
       OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
-      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
-        Record *RC = OperandInfo[i];
-        // FIXME: We only care about register operands for now.
-        if (RC && RC->isSubClassOf("RegisterClass"))
-          OS << "{ &" << getQualifiedName(RC) << "RegClass, 0 }, ";
-        else if (RC && RC->getName() == "ptr_rc")
-          // Ptr value whose register class is resolved via callback.
-          OS << "{ 0, 1 }, ";
-        else
-          OS << "{ 0, 0 }, ";
-      }
+      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+        OS << "{ " << OperandInfo[i] << " }, ";
       OS << "};\n";
     }
   }
@@ -165,7 +184,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
-                               std::map<std::vector<Record*>, unsigned> &OpInfo,
+                           std::map<std::vector<std::string>, unsigned> &OpInfo,
                                   std::ostream &OS) {
   int MinOperands;
   if (!Inst.OperandList.empty())
@@ -214,6 +233,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
   if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
   if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
+  if (Inst.isPredicated) OS << "|M_PREDICATED";
   if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
   if (Inst.isCommutable) OS << "|M_COMMUTABLE";
   if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
@@ -239,18 +259,18 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   // Emit the implicit uses and defs lists...
   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
   if (UseList.empty())
-    OS << "EmptyImpList, ";
+    OS << "NULL, ";
   else
     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 
   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
   if (DefList.empty())
-    OS << "EmptyImpList, ";
+    OS << "NULL, ";
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
   // Emit the operand info.
-  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
     OS << "0";
   else