//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
-#include "InstrInfoEmitter.h"
+
+#include "CodeGenDAGPatterns.h"
+#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
-#include "Record.h"
+#include "SequenceToOffsetTable.h"
+#include "TableGenBackends.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
+#include <cstdio>
+#include <map>
+#include <vector>
using namespace llvm;
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
- EmitSourceFileHeader("Target Instruction Enum Values", OS);
- OS << "namespace llvm {\n\n";
-
- CodeGenTarget Target;
+namespace {
+class InstrInfoEmitter {
+ RecordKeeper &Records;
+ CodeGenDAGPatterns CDP;
+ const CodeGenSchedModels &SchedModels;
+
+public:
+ InstrInfoEmitter(RecordKeeper &R):
+ Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
+
+ // run - Output the instruction set description.
+ void run(raw_ostream &OS);
+
+private:
+ void emitEnums(raw_ostream &OS);
+
+ typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
+
+ /// The keys of this map are maps which have OpName enum values as their keys
+ /// and instruction operand indices as their values. The values of this map
+ /// are lists of instruction names.
+ typedef std::map<std::map<unsigned, unsigned>,
+ std::vector<std::string> > OpNameMapTy;
+ typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
+ void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
+ Record *InstrInfo,
+ std::map<std::vector<Record*>, unsigned> &EL,
+ const OperandInfoMapTy &OpInfo,
+ raw_ostream &OS);
+ void initOperandMapData(
+ const std::vector<const CodeGenInstruction *> NumberedInstructions,
+ const std::string &Namespace,
+ std::map<std::string, unsigned> &Operands,
+ OpNameMapTy &OperandMap);
+ void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions);
+
+ // Operand information.
+ void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
+ std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
+};
+} // End anonymous namespace
- // We must emit the PHI opcode first...
- Record *InstrInfo = Target.getInstructionSet();
+static void PrintDefList(const std::vector<Record*> &Uses,
+ unsigned Num, raw_ostream &OS) {
+ OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ OS << getQualifiedName(Uses[i]) << ", ";
+ OS << "0 };\n";
+}
- std::string Namespace = Target.inst_begin()->second.Namespace;
+//===----------------------------------------------------------------------===//
+// Operand Info Emission.
+//===----------------------------------------------------------------------===//
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << " enum {\n";
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+ std::vector<std::string> Result;
+
+ for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
+ // Handle aggregate operands and normal operands the same way by expanding
+ // either case into a list of operands for this op.
+ std::vector<CGIOperandList::OperandInfo> OperandList;
+
+ // This might be a multiple operand thing. Targets like X86 have
+ // registers in their multi-operand operands. It may also be an anonymous
+ // operand, which has a single operand, but no declared class for the
+ // operand.
+ DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
+
+ if (!MIOI || MIOI->getNumArgs() == 0) {
+ // Single, anonymous, operand.
+ OperandList.push_back(Inst.Operands[i]);
+ } else {
+ for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
+ OperandList.push_back(Inst.Operands[i]);
+
+ Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
+ OperandList.back().Rec = OpR;
+ }
+ }
- std::vector<const CodeGenInstruction*> NumberedInstructions;
- Target.getInstructionsByEnumValue(NumberedInstructions);
+ for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+ Record *OpR = OperandList[j].Rec;
+ std::string Res;
+
+ if (OpR->isSubClassOf("RegisterOperand"))
+ OpR = OpR->getValueAsDef("RegClass");
+ if (OpR->isSubClassOf("RegisterClass"))
+ Res += getQualifiedName(OpR) + "RegClassID, ";
+ else if (OpR->isSubClassOf("PointerLikeRegClass"))
+ Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
+ else
+ // -1 means the operand does not have a fixed register class.
+ Res += "-1, ";
+
+ // Fill in applicable flags.
+ Res += "0";
+
+ // Ptr value whose register class is resolved via callback.
+ if (OpR->isSubClassOf("PointerLikeRegClass"))
+ Res += "|(1<<MCOI::LookupPtrRegClass)";
+
+ // Predicate operands. Check to see if the original unexpanded operand
+ // was of type PredicateOperand.
+ if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
+ Res += "|(1<<MCOI::Predicate)";
+
+ // Optional def operands. Check to see if the original unexpanded operand
+ // was of type OptionalDefOperand.
+ if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
+ Res += "|(1<<MCOI::OptionalDef)";
+
+ // Fill in operand type.
+ Res += ", MCOI::";
+ assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
+ Res += Inst.Operands[i].OperandType;
+
+ // Fill in constraint info.
+ Res += ", ";
+
+ const CGIOperandList::ConstraintInfo &Constraint =
+ Inst.Operands[i].Constraints[j];
+ if (Constraint.isNone())
+ Res += "0";
+ else if (Constraint.isEarlyClobber())
+ Res += "(1 << MCOI::EARLY_CLOBBER)";
+ else {
+ assert(Constraint.isTied());
+ Res += "((" + utostr(Constraint.getTiedOperand()) +
+ " << 16) | (1 << MCOI::TIED_TO))";
+ }
- for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
- OS << " " << NumberedInstructions[i]->TheDef->getName()
- << ", \t// " << i << "\n";
+ Result.push_back(Res);
+ }
}
- OS << " INSTRUCTION_LIST_END\n";
- OS << " };\n";
- if (!Namespace.empty())
- OS << "}\n";
- OS << "} // End llvm namespace \n";
+
+ return Result;
}
-void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
- unsigned Num, std::ostream &OS) const {
- OS << "static const unsigned ImplicitList" << Num << "[] = { ";
- for (unsigned i = 0, e = Uses.size(); i != e; ++i)
- OS << getQualifiedName(Uses[i]) << ", ";
- OS << "0 };\n";
+void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
+ OperandInfoMapTy &OperandInfoIDs) {
+ // ID #0 is for no operand info.
+ unsigned OperandListNum = 0;
+ OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+
+ OS << "\n";
+ const CodeGenTarget &Target = CDP.getTargetInfo();
+ for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+ E = Target.inst_end(); II != E; ++II) {
+ std::vector<std::string> OperandInfo = GetOperandInfo(**II);
+ unsigned &N = OperandInfoIDs[OperandInfo];
+ if (N != 0) continue;
+
+ N = ++OperandListNum;
+ OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
+ OS << "};\n";
+ }
}
-static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
- std::vector<Record*> Result;
- if (Inst.hasVariableNumberOfOperands)
- return Result; // No info for variable operand instrs.
-
- for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
- if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
- Result.push_back(Inst.OperandList[i].Rec);
- else {
- // This might be a multiple operand thing.
- // FIXME: Targets like X86 have registers in their multi-operand operands.
- for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
- Result.push_back(0);
+
+/// Initialize data structures for generating operand name mappings.
+///
+/// \param Operands [out] A map used to generate the OpName enum with operand
+/// names as its keys and operand enum values as its values.
+/// \param OperandMap [out] A map for representing the operand name mappings for
+/// each instructions. This is used to generate the OperandMap table as
+/// well as the getNamedOperandIdx() function.
+void InstrInfoEmitter::initOperandMapData(
+ const std::vector<const CodeGenInstruction *> NumberedInstructions,
+ const std::string &Namespace,
+ std::map<std::string, unsigned> &Operands,
+ OpNameMapTy &OperandMap) {
+
+ unsigned NumOperands = 0;
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ const CodeGenInstruction *Inst = NumberedInstructions[i];
+ if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) {
+ continue;
+ }
+ std::map<unsigned, unsigned> OpList;
+ for (unsigned j = 0, je = Inst->Operands.size(); j != je; ++j) {
+ const CGIOperandList::OperandInfo &Info = Inst->Operands[j];
+ StrUintMapIter I = Operands.find(Info.Name);
+
+ if (I == Operands.end()) {
+ I = Operands.insert(Operands.begin(),
+ std::pair<std::string, unsigned>(Info.Name, NumOperands++));
+ }
+ OpList[I->second] = Info.MIOperandNo;
}
+ OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName());
}
- return Result;
}
+/// Generate a table and function for looking up the indices of operands by
+/// name.
+///
+/// This code generates:
+/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
+/// for each operand name.
+/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
+/// operand indices.
+/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
+/// for looking up the operand index for an instruction, given a value from
+/// OpName enum
+void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
+ const CodeGenTarget &Target,
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions) {
+
+ const std::string &Namespace = Target.getInstNamespace();
+ std::string OpNameNS = "OpName";
+ // Map of operand names to their enumeration value. This will be used to
+ // generate the OpName enum.
+ std::map<std::string, unsigned> Operands;
+ OpNameMapTy OperandMap;
+
+ initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
+
+ OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
+ OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
+ OS << "namespace llvm {";
+ OS << "namespace " << Namespace << " {\n";
+ OS << "namespace " << OpNameNS << " { \n";
+ OS << "enum {\n";
+ for (StrUintMapIter i = Operands.begin(), e = Operands.end(); i != e; ++i)
+ OS << " " << i->first << " = " << i->second << ",\n";
+
+ OS << "OPERAND_LAST";
+ OS << "\n};\n";
+ OS << "} // End namespace OpName\n";
+ OS << "} // End namespace " << Namespace << "\n";
+ OS << "} // End namespace llvm\n";
+ OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n";
+
+ OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
+ OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
+ OS << "namespace llvm {";
+ OS << "namespace " << Namespace << " {\n";
+ OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
+ OS << " static const int16_t OperandMap []["<< Operands.size() << "] = {\n";
+ for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end();
+ i != e; ++i) {
+ const std::map<unsigned, unsigned> &OpList = i->first;
+ OS << "{";
+
+ // Emit a row of the OperandMap table
+ for (unsigned ii = 0, ie = Operands.size(); ii != ie; ++ii)
+ OS << (OpList.count(ii) == 0 ? -1 : (int)OpList.find(ii)->second) << ", ";
+
+ OS << "},\n";
+ }
+ OS << "};\n";
+
+ OS << " switch(Opcode) {\n";
+ unsigned TableIndex = 0;
+ for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end();
+ i != e; ++i) {
+ std::vector<std::string> &OpcodeList = i->second;
+
+ for (unsigned ii = 0, ie = OpcodeList.size(); ii != ie; ++ii)
+ OS << " case " << OpcodeList[ii] << ":\n";
+
+ OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
+ }
+ OS << " default: return -1;\n";
+ OS << " }\n";
+ OS << "}\n";
+ OS << "} // End namespace " << Namespace << "\n";
+ OS << "} // End namespace llvm\n";
+ OS << "#endif //GET_INSTRINFO_NAMED_OPS\n";
+
+}
+
+//===----------------------------------------------------------------------===//
+// Main Output.
+//===----------------------------------------------------------------------===//
// run - Emit the main instruction description records for the target...
-void InstrInfoEmitter::run(std::ostream &OS) {
- GatherItinClasses();
+void InstrInfoEmitter::run(raw_ostream &OS) {
+ emitSourceFileHeader("Target Instruction Enum Values", OS);
+ emitEnums(OS);
+
+ emitSourceFileHeader("Target Instruction Descriptors", OS);
+
+ OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
+ OS << "#undef GET_INSTRINFO_MC_DESC\n";
- EmitSourceFileHeader("Target Instruction Descriptors", OS);
OS << "namespace llvm {\n\n";
- CodeGenTarget Target;
+ CodeGenTarget &Target = CDP.getTargetInfo();
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
- Record *PHI = InstrInfo->getValueAsDef("PHIInst");
-
- // Emit empty implicit uses and defs lists
- OS << "static const unsigned EmptyImpList[] = { 0 };\n";
// Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists;
unsigned ListNumber = 0;
-
+
// Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- Record *Inst = II->second.TheDef;
+ Record *Inst = (*II)->TheDef;
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
if (!Uses.empty()) {
unsigned &IL = EmittedLists[Uses];
- if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
}
std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
if (!Defs.empty()) {
unsigned &IL = EmittedLists[Defs];
- if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
+ if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
}
}
- std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
- unsigned OperandListNum = 0;
- OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
-
+ OperandInfoMapTy OperandInfoIDs;
+
// Emit all of the operand info records.
- OS << "\n";
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
- std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
- unsigned &N = OperandInfosEmitted[OperandInfo];
- if (N == 0) {
- N = ++OperandListNum;
- OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
- for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
- if (Record *RC = OperandInfo[i]) {
- OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
- } else {
- OS << "{ 0 }, ";
- }
- }
- OS << "};\n";
- }
- }
-
- // Emit all of the TargetInstrDescriptor records.
+ EmitOperandInfo(OS, OperandInfoIDs);
+
+ // Emit all of the MCInstrDesc records in their ENUM ordering.
//
- OS << "\nstatic const TargetInstrDescriptor " << TargetName
- << "Insts[] = {\n";
- emitRecord(Target.getPHIInstruction(), 0, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
+ OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
+
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
+ emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
+ OperandInfoIDs, OS);
+ OS << "};\n\n";
+
+ // Build an array of instruction names
+ SequenceToOffsetTable<std::string> InstrNames;
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ const CodeGenInstruction *Instr = NumberedInstructions[i];
+ InstrNames.add(Instr->TheDef->getName());
+ }
+
+ InstrNames.layout();
+ OS << "extern const char " << TargetName << "InstrNameData[] = {\n";
+ InstrNames.emit(OS, printChar);
+ OS << "};\n\n";
+
+ OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ if (i % 8 == 0)
+ OS << "\n ";
+ const CodeGenInstruction *Instr = NumberedInstructions[i];
+ OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
+ }
+
+ OS << "\n};\n\n";
+
+ // MCInstrInfo initialization routine.
+ OS << "static inline void Init" << TargetName
+ << "MCInstrInfo(MCInstrInfo *II) {\n";
+ OS << " II->InitMCInstrInfo(" << TargetName << "Insts, "
+ << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
+ << NumberedInstructions.size() << ");\n}\n\n";
- unsigned i = 0;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II)
- if (II->second.TheDef != PHI)
- emitRecord(II->second, ++i, InstrInfo, EmittedLists,
- OperandInfosEmitted, OS);
- OS << "};\n";
OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
+
+ // Create a TargetInstrInfo subclass to hide the MC layer initialization.
+ OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
+ OS << "#undef GET_INSTRINFO_HEADER\n";
+
+ std::string ClassName = TargetName + "GenInstrInfo";
+ OS << "namespace llvm {\n";
+ OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
+ << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
+ << "};\n";
+ OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_HEADER\n\n";
+
+ OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
+ OS << "#undef GET_INSTRINFO_CTOR\n";
+
+ OS << "namespace llvm {\n";
+ OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
+ OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
+ OS << "extern const char " << TargetName << "InstrNameData[];\n";
+ OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
+ << " : TargetInstrInfo(SO, DO) {\n"
+ << " InitMCInstrInfo(" << TargetName << "Insts, "
+ << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, "
+ << NumberedInstructions.size() << ");\n}\n";
+ OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_CTOR\n\n";
+
+ emitOperandNameMappings(OS, Target, NumberedInstructions);
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EmittedLists,
- std::map<std::vector<Record*>, unsigned> &OpInfo,
- std::ostream &OS) {
- int NumOperands;
- if (Inst.hasVariableNumberOfOperands)
- NumOperands = -1;
- else if (!Inst.OperandList.empty())
+ const OperandInfoMapTy &OpInfo,
+ raw_ostream &OS) {
+ int MinOperands = 0;
+ if (!Inst.Operands.empty())
// Each logical operand can be multiple MI operands.
- NumOperands = Inst.OperandList.back().MIOperandNo +
- Inst.OperandList.back().MINumOperands;
- else
- NumOperands = 0;
-
- OS << " { \"";
- if (Inst.Name.empty())
- OS << Inst.TheDef->getName();
- else
- OS << Inst.Name;
-
- unsigned ItinClass = !IsItineraries ? 0 :
- ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
-
- OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, "
- << ItinClass
- << ", 0";
+ MinOperands = Inst.Operands.back().MIOperandNo +
+ Inst.Operands.back().MINumOperands;
+
+ OS << " { ";
+ OS << Num << ",\t" << MinOperands << ",\t"
+ << Inst.Operands.NumDefs << ",\t"
+ << SchedModels.getSchedClassIdx(Inst) << ",\t"
+ << Inst.TheDef->getValueAsInt("Size") << ",\t0";
// Emit all of the target indepedent flags...
- if (Inst.isReturn) OS << "|M_RET_FLAG";
- if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
- if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
- if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
- if (Inst.isCall) OS << "|M_CALL_FLAG";
- if (Inst.isLoad) OS << "|M_LOAD_FLAG";
- if (Inst.isStore) OS << "|M_STORE_FLAG";
- if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
- if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
- if (Inst.isCommutable) OS << "|M_COMMUTABLE";
- if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
- if (Inst.usesCustomDAGSchedInserter)
- OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
- OS << ", 0";
+ if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)";
+ if (Inst.isReturn) OS << "|(1<<MCID::Return)";
+ if (Inst.isBranch) OS << "|(1<<MCID::Branch)";
+ if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)";
+ if (Inst.isCompare) OS << "|(1<<MCID::Compare)";
+ if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)";
+ if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)";
+ if (Inst.isSelect) OS << "|(1<<MCID::Select)";
+ if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)";
+ if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)";
+ if (Inst.isCall) OS << "|(1<<MCID::Call)";
+ if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)";
+ if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)";
+ if (Inst.mayStore) OS << "|(1<<MCID::MayStore)";
+ if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)";
+ if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)";
+ if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)";
+ if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)";
+ if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)";
+ if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)";
+ if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)";
+ if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)";
+ if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)";
+ if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)";
+ if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)";
+ if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)";
+ if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)";
+ if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)";
// Emit all of the target-specific flags...
- ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
- ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
- if (LI->getSize() != Shift->getSize())
- throw "Lengths of " + InstrInfo->getName() +
- ":(TargetInfoFields, TargetInfoPositions) must be equal!";
-
- for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
- emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
- dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
-
- OS << ", ";
+ BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
+ if (!TSF)
+ PrintFatalError("no TSFlags?");
+ uint64_t Value = 0;
+ for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
+ if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
+ Value |= uint64_t(Bit->getValue()) << i;
+ else
+ PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
+ }
+ OS << ", 0x";
+ OS.write_hex(Value);
+ OS << "ULL, ";
// Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
// Emit the operand info.
- std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+ std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
OS << "0";
else
- OS << "OperandInfo" << OpInfo[OperandInfo];
-
+ OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
+
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
}
-struct LessRecord {
- bool operator()(const Record *Rec1, const Record *Rec2) const {
- return Rec1->getName() < Rec2->getName();
- }
-};
-void InstrInfoEmitter::GatherItinClasses() {
- std::vector<Record*> DefList =
- Records.getAllDerivedDefinitions("InstrItinClass");
- IsItineraries = !DefList.empty();
-
- if (!IsItineraries) return;
-
- sort(DefList.begin(), DefList.end(), LessRecord());
-
- for (unsigned i = 0, N = DefList.size(); i < N; i++) {
- Record *Def = DefList[i];
- ItinClassMap[Def->getName()] = i + 1;
+// emitEnums - Print out enum values for all of the instructions.
+void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
+
+ OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
+ OS << "#undef GET_INSTRINFO_ENUM\n";
+
+ OS << "namespace llvm {\n\n";
+
+ CodeGenTarget Target(Records);
+
+ // We must emit the PHI opcode first...
+ std::string Namespace = Target.getInstNamespace();
+
+ if (Namespace.empty()) {
+ fprintf(stderr, "No instructions defined!\n");
+ exit(1);
}
-}
-
-unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
- return ItinClassMap[ItinName];
-}
-void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
- IntInit *ShiftInt, std::ostream &OS) {
- if (Val == 0 || ShiftInt == 0)
- throw std::string("Illegal value or shift amount in TargetInfo*!");
- RecordVal *RV = R->getValue(Val->getValue());
- int Shift = ShiftInt->getValue();
-
- if (RV == 0 || RV->getValue() == 0)
- throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
-
- Init *Value = RV->getValue();
- if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
- if (BI->getValue()) OS << "|(1<<" << Shift << ")";
- return;
- } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
- // Convert the Bits to an integer to print...
- Init *I = BI->convertInitializerTo(new IntRecTy());
- if (I)
- if (IntInit *II = dynamic_cast<IntInit*>(I)) {
- if (II->getValue())
- OS << "|(" << II->getValue() << "<<" << Shift << ")";
- return;
- }
+ const std::vector<const CodeGenInstruction*> &NumberedInstructions =
+ Target.getInstructionsByEnumValue();
- } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
- if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
- return;
+ OS << "namespace " << Namespace << " {\n";
+ OS << " enum {\n";
+ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
+ OS << " " << NumberedInstructions[i]->TheDef->getName()
+ << "\t= " << i << ",\n";
}
+ OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
+ OS << " };\n}\n";
+ OS << "} // End llvm namespace \n";
+
+ OS << "#endif // GET_INSTRINFO_ENUM\n\n";
+}
+
+namespace llvm {
- std::cerr << "Unhandled initializer: " << *Val << "\n";
- throw "In record '" + R->getName() + "' for TSFlag emission.";
+void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
+ InstrInfoEmitter(RK).run(OS);
+ EmitMapTable(RK, OS);
}
+} // End llvm namespace
projects / oota-llvm.git / blobdiff