#include "InstrInfoEmitter.h"
#include "CodeGenTarget.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "Record.h"
#include <algorithm>
using namespace llvm;
CodeGenTarget Target;
// We must emit the PHI opcode first...
- Record *InstrInfo = Target.getInstructionSet();
-
std::string Namespace;
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
}
if (Namespace.empty()) {
- std::cerr << "No instructions defined!\n";
+ cerr << "No instructions defined!\n";
exit(1);
}
OS << "0 };\n";
}
-static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
- std::vector<Record*> Result;
- if (Inst.hasVariableNumberOfOperands)
- return Result; // No info for variable operand instrs.
-
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+ std::vector<std::string> Result;
+
for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
- if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
- Result.push_back(Inst.OperandList[i].Rec);
+ // Handle aggregate operands and normal operands the same way by expanding
+ // either case into a list of operands for this op.
+ std::vector<CodeGenInstruction::OperandInfo> OperandList;
+
+ // This might be a multiple operand thing. Targets like X86 have
+ // registers in their multi-operand operands. It may also be an anonymous
+ // operand, which has a single operand, but no declared class for the
+ // operand.
+ DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+
+ if (!MIOI || MIOI->getNumArgs() == 0) {
+ // Single, anonymous, operand.
+ OperandList.push_back(Inst.OperandList[i]);
} else {
- // This might be a multiple operand thing.
- // Targets like X86 have registers in their multi-operand operands.
- DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
- unsigned NumDefs = MIOI->getNumArgs();
for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
- if (NumDefs <= j) {
- Result.push_back(0);
- } else {
- DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
- Result.push_back(Def ? Def->getDef() : 0);
- }
+ OperandList.push_back(Inst.OperandList[i]);
+
+ Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
+ OperandList.back().Rec = OpR;
}
}
+
+ for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+ Record *OpR = OperandList[j].Rec;
+ std::string Res;
+
+ if (OpR->isSubClassOf("RegisterClass"))
+ Res += getQualifiedName(OpR) + "RegClassID, ";
+ else
+ Res += "0, ";
+ // Fill in applicable flags.
+ Res += "0";
+
+ // Ptr value whose register class is resolved via callback.
+ if (OpR->getName() == "ptr_rc")
+ Res += "|M_LOOK_UP_PTR_REG_CLASS";
+
+ // Predicate operands. Check to see if the original unexpanded operand
+ // was of type PredicateOperand.
+ if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+ Res += "|M_PREDICATE_OPERAND";
+
+ // Fill in constraint info.
+ Res += ", " + Inst.OperandList[i].Constraints[j];
+ Result.push_back(Res);
+ }
}
+
return Result;
}
const std::string &TargetName = Target.getName();
Record *InstrInfo = Target.getInstructionSet();
- // Emit empty implicit uses and defs lists
- OS << "static const unsigned EmptyImpList[] = { 0 };\n";
-
// Keep track of all of the def lists we have emitted already.
std::map<std::vector<Record*>, unsigned> EmittedLists;
unsigned ListNumber = 0;
}
}
- std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
+ std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
unsigned OperandListNum = 0;
- OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+ OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
// Emit all of the operand info records.
OS << "\n";
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
+ std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
unsigned &N = OperandInfosEmitted[OperandInfo];
if (N == 0) {
N = ++OperandListNum;
OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
- for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
- Record *RC = OperandInfo[i];
- // FIXME: We only care about register operands for now.
- if (RC && RC->isSubClassOf("RegisterClass")) {
- OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
- } else {
- OS << "{ 0 }, ";
- }
- }
+ for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+ OS << "{ " << OperandInfo[i] << " }, ";
OS << "};\n";
}
}
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
Record *InstrInfo,
std::map<std::vector<Record*>, unsigned> &EmittedLists,
- std::map<std::vector<Record*>, unsigned> &OpInfo,
+ std::map<std::vector<std::string>, unsigned> &OpInfo,
std::ostream &OS) {
- int NumOperands;
- if (Inst.hasVariableNumberOfOperands)
- NumOperands = -1;
- else if (!Inst.OperandList.empty())
+ int MinOperands;
+ if (!Inst.OperandList.empty())
// Each logical operand can be multiple MI operands.
- NumOperands = Inst.OperandList.back().MIOperandNo +
+ MinOperands = Inst.OperandList.back().MIOperandNo +
Inst.OperandList.back().MINumOperands;
else
- NumOperands = 0;
+ MinOperands = 0;
- OS << " { \"";
+ OS << " { ";
+ OS << Num << ",\t" << MinOperands << ",\t\"";
+
if (Inst.Name.empty())
OS << Inst.TheDef->getName();
else
unsigned ItinClass = !IsItineraries ? 0 :
ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
- OS << "\",\t" << NumOperands << ", " << ItinClass
- << ", 0";
+ OS << "\",\t" << ItinClass << ", 0";
// Try to determine (from the pattern), if the instruction is a store.
bool isStore = false;
DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
if (OpDef) {
Record *Operator = OpDef->getDef();
- if (Operator->isSubClassOf("SDNode") &&
- Operator->getValueAsString("Opcode") == "ISD::STORE")
- isStore = true;
+ if (Operator->isSubClassOf("SDNode")) {
+ const std::string Opcode = Operator->getValueAsString("Opcode");
+ if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
+ isStore = true;
+ }
}
}
}
if (Inst.isCall) OS << "|M_CALL_FLAG";
if (Inst.isLoad) OS << "|M_LOAD_FLAG";
if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
- if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
+ if (Inst.isPredicated) OS << "|M_PREDICATED";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
+ if (Inst.hasVariableNumberOfOperands)
+ OS << "|M_VARIABLE_OPS";
OS << ", 0";
// Emit all of the target-specific flags...
// Emit the implicit uses and defs lists...
std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
if (UseList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[UseList] << ", ";
std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
if (DefList.empty())
- OS << "EmptyImpList, ";
+ OS << "NULL, ";
else
OS << "ImplicitList" << EmittedLists[DefList] << ", ";
// Emit the operand info.
- std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+ std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
if (OperandInfo.empty())
OS << "0";
else
return;
}
- std::cerr << "Unhandled initializer: " << *Val << "\n";
+ cerr << "Unhandled initializer: " << *Val << "\n";
throw "In record '" + R->getName() + "' for TSFlag emission.";
}
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