Change from llvm::SmallSet<std::string> to llvm::StringMap<char>.

[oota-llvm.git] / utils / TableGen / InstrInfoEmitter.cpp

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 3f2b49fda659c2ad873cde5712f44ed8e25b6e57..57d72b436e3b991034fb0744c95a2fbc9d3fff13 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -94,17 +94,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
         
       // Ptr value whose register class is resolved via callback.
       if (OpR->getName() == "ptr_rc")
-        Res += "|M_LOOK_UP_PTR_REG_CLASS";
+        Res += "|(1<<TOI::LookupPtrRegClass)";
 
       // Predicate operands.  Check to see if the original unexpanded operand
       // was of type PredicateOperand.
       if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
-        Res += "|M_PREDICATE_OPERAND";
+        Res += "|(1<<TOI::Predicate)";
         
       // Optional def operands.  Check to see if the original unexpanded operand
       // was of type OptionalDefOperand.
       if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
-        Res += "|M_OPTIONAL_DEF_OPERAND";
+        Res += "|(1<<TOI::OptionalDef)";
 
       // Fill in constraint info.
       Res += ", " + Inst.OperandList[i].Constraints[j];
@@ -148,7 +148,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   EmitSourceFileHeader("Target Instruction Descriptors", OS);
   OS << "namespace llvm {\n\n";
 
-  CodeGenTarget Target;
+  CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
 
@@ -177,9 +177,9 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   // Emit all of the operand info records.
   EmitOperandInfo(OS, OperandInfoIDs);
   
-  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
+  // Emit all of the TargetInstrDesc records in their ENUM ordering.
   //
-  OS << "\nstatic const TargetInstrDescriptor " << TargetName
+  OS << "\nstatic const TargetInstrDesc " << TargetName
      << "Insts[] = {\n";
   std::vector<const CodeGenInstruction*> NumberedInstructions;
   Target.getInstructionsByEnumValue(NumberedInstructions);
@@ -196,65 +196,38 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
                                   const OperandInfoMapTy &OpInfo,
                                   std::ostream &OS) {
-  int MinOperands;
+  int MinOperands = 0;
   if (!Inst.OperandList.empty())
     // Each logical operand can be multiple MI operands.
     MinOperands = Inst.OperandList.back().MIOperandNo +
                   Inst.OperandList.back().MINumOperands;
-  else
-    MinOperands = 0;
   
   OS << "  { ";
   OS << Num << ",\t" << MinOperands << ",\t"
-     << Inst.NumDefs << ",\t\"";
-
-  if (Inst.Name.empty())
-    OS << Inst.TheDef->getName();
-  else
-    OS << Inst.Name;
-  
-  OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0";
-
-  // Try to determine (from the pattern), if the instruction is a store.
-  bool isStore = false;
-  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
-    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
-    if (LI && LI->getSize() > 0) {
-      DagInit *Dag = (DagInit *)LI->getElement(0);
-      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
-      if (OpDef) {
-        Record *Operator = OpDef->getDef();
-        if (Operator->isSubClassOf("SDNode")) {
-          const std::string Opcode = Operator->getValueAsString("Opcode");
-          if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
-            isStore = true;
-        }
-      }
-    }
-  }
+     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
+     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
 
   // Emit all of the target indepedent flags...
-  if (Inst.isReturn)     OS << "|M_RET_FLAG";
-  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
-  if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG";
-  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
-  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
-  if (Inst.isCall)       OS << "|M_CALL_FLAG";
-  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
-  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
-  if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
-  if (Inst.isPredicable) OS << "|M_PREDICABLE";
-  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
-  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
-  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
-  if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
-  if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE";
-  if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
+  if (Inst.isReturn)     OS << "|(1<<TID::Return)";
+  if (Inst.isBranch)     OS << "|(1<<TID::Branch)";
+  if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+  if (Inst.isBarrier)    OS << "|(1<<TID::Barrier)";
+  if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
+  if (Inst.isCall)       OS << "|(1<<TID::Call)";
+  if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
+  if (Inst.mayLoad)      OS << "|(1<<TID::MayLoad)";
+  if (Inst.mayStore)     OS << "|(1<<TID::MayStore)";
+  if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
+  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
+  if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
+  if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
+  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
+  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
+  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
   if (Inst.usesCustomDAGSchedInserter)
-    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
-  if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
-  if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
-  if (Inst.neverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
+    OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
+  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
+  if (Inst.hasSideEffects)          OS << "|(1<<TID::UnmodeledSideEffects)";
   OS << ", 0";
 
   // Emit all of the target-specific flags...
@@ -306,8 +279,11 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
     if (R->getName() != "PHI" &&
         R->getName() != "INLINEASM" &&
         R->getName() != "LABEL" &&
+        R->getName() != "DECLARE" &&
         R->getName() != "EXTRACT_SUBREG" &&
-        R->getName() != "INSERT_SUBREG")
+        R->getName() != "INSERT_SUBREG" &&
+        R->getName() != "IMPLICIT_DEF" &&
+        R->getName() != "SUBREG_TO_REG")
       throw R->getName() + " doesn't have a field named '" + 
             Val->getValue() + "'!";
     return;