implement new method

[oota-llvm.git] / utils / TableGen / InstrSelectorEmitter.cpp

diff --git a/utils/TableGen/InstrSelectorEmitter.cpp b/utils/TableGen/InstrSelectorEmitter.cpp
index 8bc8f611dd2b50420d75d7cf54b260f23b0998c1..5c0939352477fe77207d02ab48781adb659cd1b1 100644 (file)
--- a/utils/TableGen/InstrSelectorEmitter.cpp
+++ b/utils/TableGen/InstrSelectorEmitter.cpp
@@ -1,4 +1,11 @@
 //===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This tablegen backend is responsible for emitting a description of the target
 // instruction set for the code generator.
@@ -12,6 +19,8 @@
 #include "Support/StringExtras.h"
 #include <set>
 
+namespace llvm {
+
 NodeType::ArgResultTypes NodeType::Translate(Record *R) {
   const std::string &Name = R->getName();
   if (Name == "DNVT_any")  return Any;
@@ -49,7 +58,7 @@ bool TreePatternNode::updateNodeType(MVT::ValueType VT,
     return true;
   }
 
-  throw "Type inferfence contradiction found for pattern " + RecName;
+  throw "Type inference contradiction found for pattern " + RecName;
 }
 
 /// InstantiateNonterminals - If this pattern refers to any nonterminals which
@@ -210,6 +219,7 @@ TreePatternNode *Pattern::ParseTreePattern(DagInit *Dag) {
     } else {
       Arg->dump();
       error("Unknown leaf value for tree pattern!");
+      return 0;
     }
 
     // Apply the type cast...
@@ -970,9 +980,10 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
 
   CalculateComputableValues();
   
+  OS << "#include \"llvm/CodeGen/MachineInstrBuilder.h\"\n";
+
   EmitSourceFileHeader("Instruction Selector for the " + Target.getName() +
                        " target", OS);
-  OS << "#include \"llvm/CodeGen/MachineInstrBuilder.h\"\n";
 
   // Output the slot number enums...
   OS << "\nenum { // Slot numbers...\n"
@@ -1012,7 +1023,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
      << "  class " << Target.getName() << "ISel {\n"
      << "    SelectionDAG &DAG;\n"
      << "  public:\n"
-     << "    X86ISel(SelectionDAG &D) : DAG(D) {}\n"
+     << "    " << Target.getName () << "ISel(SelectionDAG &D) : DAG(D) {}\n"
      << "    void generateCode();\n"
      << "  private:\n"
      << "    unsigned makeAnotherReg(const TargetRegisterClass *RC) {\n"
@@ -1049,7 +1060,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
   OS << "  };\n}\n\n";
 
   // Emit the generateCode entry-point...
-  OS << "void X86ISel::generateCode() {\n"
+  OS << "void " << Target.getName () << "ISel::generateCode() {\n"
      << "  SelectionDAGNode *Root = DAG.getRoot();\n"
      << "  assert(Root->getValueType() == MVT::isVoid && "
                                        "\"Root of DAG produces value??\");\n\n"
@@ -1282,5 +1293,7 @@ void InstrSelectorEmitter::run(std::ostream &OS) {
        << "  }\n\n  N->addValue(Val);  // Do not ever recalculate this\n"
        << "  return Val;\n}\n\n";
   }
+  EmitSourceFileTail(OS);
 }
 
+} // End llvm namespace