void EmitRegMappingTables(raw_ostream &o,
const std::vector<CodeGenRegister*> &Regs,
bool isCtor);
- void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
-
void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
const std::string &ClassName);
void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
OS << "}\n";
}
- const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
+ const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
// If the only definition is the default NoRegAltName, we don't need to
// emit anything.
if (RegAltNameIndices.size() > 1) {
<< "getRegPressureSetName(unsigned Idx) const {\n"
<< " static const char *PressureNameTable[] = {\n";
for (unsigned i = 0; i < NumSets; ++i ) {
- OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
+ OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
}
- OS << " 0 };\n"
+ OS << " nullptr };\n"
<< " return PressureNameTable[Idx];\n"
<< "}\n\n";
<< "getRegPressureSetLimit(unsigned Idx) const {\n"
<< " static const unsigned PressureLimitTable[] = {\n";
for (unsigned i = 0; i < NumSets; ++i ) {
- const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
- OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
- << ", \t// " << i << ": " << RegUnits.Name << "\n";
+ const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
+ OS << " " << RegUnits.Weight << ", \t// " << i << ": "
+ << RegUnits.Name << "\n";
}
OS << " 0 };\n"
<< " return PressureLimitTable[Idx];\n"
for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) {
RCSetStarts[i] = StartIdx;
ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
+ std::vector<unsigned> PSets;
+ PSets.reserve(PSetIDs.size());
for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
- OS << *PSetI << ", ";
+ PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order);
+ }
+ std::sort(PSets.begin(), PSets.end());
+ for (unsigned j = 0, e = PSets.size(); j < e; ++j) {
+ OS << PSets[j] << ", ";
++StartIdx;
}
OS << "-1, \t// #" << RCSetStarts[i] << " ";
OS << "inferred";
for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
- OS << "~" << RegBank.getRegPressureSet(*PSetI).Name;
+ OS << "~" << RegBank.getRegSetAt(*PSetI).Name;
}
}
OS << "\n ";
const std::vector<CodeGenRegister*> &Regs,
bool isCtor) {
// Collect all information about dwarf register numbers
- typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
+ typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
// First, just pull all provided information to the map
// Keep track of sub-register names as well. These are not differentially
// encoded.
typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
- SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs;
+ SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs;
SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
SequenceToOffsetTable<std::string> RegStrings;
// Emit the table of register unit roots. Each regunit has one or two root
// registers.
- OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
assert(!Roots.empty() && "All regunits must have a root register.");
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
- << " const uint16_t " << Name
+ << " const MCPhysReg " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
Record *Reg = Order[i];
uint64_t Value = 0;
for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
- Value |= (uint64_t)B->getValue() << b;
+ Value |= (uint64_t)B->getValue() << b;
}
OS << " " << Value << ",\n";
}
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName
<< "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
- << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
+ << " bool needsStackRealignment(const MachineFunction &) const override\n"
<< " { return false; }\n";
if (!RegBank.getSubRegIndices().empty()) {
- OS << " virtual unsigned composeSubRegIndicesImpl"
- << "(unsigned, unsigned) const;\n"
- << " virtual const TargetRegisterClass *"
- "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
+ OS << " unsigned composeSubRegIndicesImpl"
+ << "(unsigned, unsigned) const override;\n"
+ << " const TargetRegisterClass *getSubClassWithSubReg"
+ << "(const TargetRegisterClass*, unsigned) const override;\n";
}
- OS << " virtual const RegClassWeight &getRegClassWeight("
- << "const TargetRegisterClass *RC) const;\n"
- << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n"
- << " virtual unsigned getNumRegPressureSets() const;\n"
- << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n"
- << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
- << " virtual const int *getRegClassPressureSets("
- << "const TargetRegisterClass *RC) const;\n"
- << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n"
+ OS << " const RegClassWeight &getRegClassWeight("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
+ << " unsigned getNumRegPressureSets() const override;\n"
+ << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
+ << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
+ << " const int *getRegClassPressureSets("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " const int *getRegUnitPressureSets("
+ << "unsigned RegUnit) const override;\n"
<< "};\n\n";
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
// Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) {
OS << "\nstatic const TargetRegisterClass *const "
- << "NullRegClasses[] = { NULL };\n\n";
+ << "NullRegClasses[] = { nullptr };\n\n";
// Emit register class bit mask tables. The first bit mask emitted for a
// register class, RC, is the set of sub-classes, including RC itself.
// Compress the sub-reg index lists.
typedef std::vector<const CodeGenSubRegIndex*> IdxList;
SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
- SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
+ SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs;
BitVector MaskBV(RegisterClasses.size());
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
<< RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i)
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
- OS << " NULL\n};\n\n";
+ OS << " nullptr\n};\n\n";
}
// Emit methods.
else
OS << RC.getName() << "Superclasses,\n ";
if (RC.AltOrderSelect.empty())
- OS << "0\n";
+ OS << "nullptr\n";
else
OS << RC.getName() << "GetRawAllocationOrder\n";
OS << " };\n\n";
<< " if (!Idx) return RC;\n --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " unsigned TV = Table[RC->getID()][Idx];\n"
- << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
+ << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
}
EmitRegUnitPressure(OS, RegBank, ClassName);
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
OS << "extern const char " << TargetName << "RegStrings[];\n";
- OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
OS << "extern const MCRegisterInfo::SubRegCoveredBits "
<< TargetName << "SubRegIdxRanges[];\n";
OS << "0 };\n";
// Emit the *_RegMask bit mask of call-preserved registers.
+ BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
+
+ // Check for an optional OtherPreserved set.
+ // Add those registers to RegMask, but not to SaveList.
+ if (DagInit *OPDag =
+ dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
+ SetTheory::RecSet OPSet;
+ RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
+ Covered |= RegBank.computeCoveredRegisters(
+ ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
+ }
+
OS << "static const uint32_t " << CSRSet->getName()
<< "_RegMask[] = { ";
- printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
+ printBitVectorAsHex(OS, Covered, 32);
OS << "};\n";
}
OS << "\n\n";
projects / oota-llvm.git / blobdiff