for (unsigned i = 0; i < NumSets; ++i ) {
OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
}
- OS << " 0 };\n"
+ OS << " nullptr };\n"
<< " return PressureNameTable[Idx];\n"
<< "}\n\n";
// Emit the table of register unit roots. Each regunit has one or two root
// registers.
- OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
assert(!Roots.empty() && "All regunits must have a root register.");
// Emit the register list now.
OS << " // " << Name << " Register Class...\n"
- << " const uint16_t " << Name
+ << " const MCPhysReg " << Name
<< "[] = {\n ";
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
Record *Reg = Order[i];
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName
<< "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
- << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
+ << " bool needsStackRealignment(const MachineFunction &) const override\n"
<< " { return false; }\n";
if (!RegBank.getSubRegIndices().empty()) {
- OS << " virtual unsigned composeSubRegIndicesImpl"
- << "(unsigned, unsigned) const;\n"
- << " virtual const TargetRegisterClass *"
- "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
+ OS << " unsigned composeSubRegIndicesImpl"
+ << "(unsigned, unsigned) const override;\n"
+ << " const TargetRegisterClass *getSubClassWithSubReg"
+ << "(const TargetRegisterClass*, unsigned) const override;\n";
}
- OS << " virtual const RegClassWeight &getRegClassWeight("
- << "const TargetRegisterClass *RC) const;\n"
- << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n"
- << " virtual unsigned getNumRegPressureSets() const;\n"
- << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n"
- << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
- << " virtual const int *getRegClassPressureSets("
- << "const TargetRegisterClass *RC) const;\n"
- << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n"
+ OS << " const RegClassWeight &getRegClassWeight("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
+ << " unsigned getNumRegPressureSets() const override;\n"
+ << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
+ << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
+ << " const int *getRegClassPressureSets("
+ << "const TargetRegisterClass *RC) const override;\n"
+ << " const int *getRegUnitPressureSets("
+ << "unsigned RegUnit) const override;\n"
<< "};\n\n";
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
// Now that all of the structs have been emitted, emit the instances.
if (!RegisterClasses.empty()) {
OS << "\nstatic const TargetRegisterClass *const "
- << "NullRegClasses[] = { NULL };\n\n";
+ << "NullRegClasses[] = { nullptr };\n\n";
// Emit register class bit mask tables. The first bit mask emitted for a
// register class, RC, is the set of sub-classes, including RC itself.
<< RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i)
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
- OS << " NULL\n};\n\n";
+ OS << " nullptr\n};\n\n";
}
// Emit methods.
else
OS << RC.getName() << "Superclasses,\n ";
if (RC.AltOrderSelect.empty())
- OS << "0\n";
+ OS << "nullptr\n";
else
OS << RC.getName() << "GetRawAllocationOrder\n";
OS << " };\n\n";
<< " if (!Idx) return RC;\n --Idx;\n"
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
<< " unsigned TV = Table[RC->getID()][Idx];\n"
- << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
+ << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
}
EmitRegUnitPressure(OS, RegBank, ClassName);
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
OS << "extern const char " << TargetName << "RegStrings[];\n";
- OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
+ OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
OS << "extern const MCRegisterInfo::SubRegCoveredBits "
<< TargetName << "SubRegIdxRanges[];\n";