}
static void addSuperReg(Record *R, Record *S,
- std::map<Record*, std::set<Record*> > &SubRegs,
- std::map<Record*, std::set<Record*> > &SuperRegs,
- std::map<Record*, std::set<Record*> > &Aliases) {
+ std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
+ std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
+ std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
if (R == S) {
cerr << "Error: recursive sub-register relationship between"
<< " register " << getQualifiedName(R)
}
static void addSubSuperReg(Record *R, Record *S,
- std::map<Record*, std::set<Record*> > &SubRegs,
- std::map<Record*, std::set<Record*> > &SuperRegs,
- std::map<Record*, std::set<Record*> > &Aliases) {
+ std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
+ std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
+ std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
if (R == S) {
cerr << "Error: recursive sub-register relationship between"
<< " register " << getQualifiedName(R)
class RegisterSorter {
private:
- std::map<Record*, std::set<Record*> > &RegisterSubRegs;
+ std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
public:
- RegisterSorter(std::map<Record*, std::set<Record*> > &RS)
+ RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
: RegisterSubRegs(RS) {};
bool operator()(Record *RegA, Record *RegB) {
<< RegisterClasses[i].getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
- std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
-
- // Emit the sub-register classes for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
- OS << " // " << Name
- << " Sub-register Classess...\n"
- << " static const TargetRegisterClass* const "
- << Name << "SubRegClasses [] = {\n ";
-
- bool Empty = true;
-
- for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size();
- subrc != subrcMax; ++subrc) {
- unsigned rc2 = 0, e2 = RegisterClasses.size();
- for (; rc2 != e2; ++rc2) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
- if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
- if (!Empty)
- OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
-
- std::map<unsigned, std::set<unsigned> >::iterator SCMI =
- SuperRegClassMap.find(rc2);
- if (SCMI == SuperRegClassMap.end()) {
- SuperRegClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
- SCMI = SuperRegClassMap.find(rc2);
- }
- SCMI->second.insert(rc);
- break;
- }
- }
- if (rc2 == e2)
- throw "Register Class member '" +
- RC.SubRegClasses[subrc]->getName() +
- "' is not a valid RegisterClass!";
- }
-
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
- }
-
- // Emit the super-register classes for each RegisterClass
- for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
- const CodeGenRegisterClass &RC = RegisterClasses[rc];
-
- // Give the register class a legal C name if it's anonymous.
- std::string Name = RC.TheDef->getName();
-
- OS << " // " << Name
- << " Super-register Classess...\n"
- << " static const TargetRegisterClass* const "
- << Name << "SuperRegClasses [] = {\n ";
-
- bool Empty = true;
- std::map<unsigned, std::set<unsigned> >::iterator I =
- SuperRegClassMap.find(rc);
- if (I != SuperRegClassMap.end()) {
- for (std::set<unsigned>::iterator II = I->second.begin(),
- EE = I->second.end(); II != EE; ++II) {
- const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
- if (!Empty)
- OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
- }
- }
-
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
- }
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
- << RC.getName() + "SubRegClasses" << ", "
- << RC.getName() + "SuperRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
OS << " };\n";
// Emit register sub-registers / super-registers, aliases...
- std::map<Record*, std::set<Record*> > RegisterSubRegs;
- std::map<Record*, std::set<Record*> > RegisterSuperRegs;
- std::map<Record*, std::set<Record*> > RegisterAliases;
+ std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
+ std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
+ std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
- std::map<Record*, std::vector<int> > DwarfRegNums;
+ typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
+ DwarfRegNumsMapTy DwarfRegNums;
const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
RegisterAliases);
}
}
+
+ // Print the SubregHashTable, a simple quadratically probed
+ // hash table for determining if a register is a subregister
+ // of another register.
+ unsigned NumSubRegs = 0;
+ std::map<Record*, unsigned> RegNo;
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ RegNo[Regs[i].TheDef] = i;
+ NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
+ }
+
+ unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
+ unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
+ std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
+
+ unsigned hashMisses = 0;
+
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record* R = Regs[i].TheDef;
+ for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
+ E = RegisterSubRegs[R].end(); I != E; ++I) {
+ Record* RJ = *I;
+ // We have to increase the indices of both registers by one when
+ // computing the hash because, in the generated code, there
+ // will be an extra empty slot at register 0.
+ size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
+ unsigned ProbeAmt = 2;
+ while (SubregHashTable[index*2] != ~0U &&
+ SubregHashTable[index*2+1] != ~0U) {
+ index = (index + ProbeAmt) & (SubregHashTableSize-1);
+ ProbeAmt += 2;
+
+ hashMisses++;
+ }
+
+ SubregHashTable[index*2] = i;
+ SubregHashTable[index*2+1] = RegNo[RJ];
+ }
+ }
+
+ OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
+
+ if (SubregHashTableSize) {
+ std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
+
+ OS << " const unsigned SubregHashTable[] = { ";
+ for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
+ if (i != 0)
+ // Insert spaces for nice formatting.
+ OS << " ";
+
+ if (SubregHashTable[2*i] != ~0U) {
+ OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
+ << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
+ }
+ }
+
+ unsigned Idx = SubregHashTableSize*2-2;
+ if (SubregHashTable[Idx] != ~0U) {
+ OS << " "
+ << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
+ << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
+ } else {
+ OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
+ }
+
+ OS << " const unsigned SubregHashTableSize = "
+ << SubregHashTableSize << ";\n";
+ } else {
+ OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
+ << " const unsigned SubregHashTableSize = 1;\n";
+ }
+
+ delete [] SubregHashTable;
if (!RegisterAliases.empty())
OS << "\n\n // Register Alias Sets...\n";
OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
// Loop over all of the registers which have aliases, emitting the alias list
// to memory.
- for (std::map<Record*, std::set<Record*> >::iterator
+ for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
for (std::set<Record*>::iterator ASI = I->second.begin(),
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
- for (std::map<Record*, std::set<Record*> >::iterator
+ for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
std::vector<Record*> SubRegsVector;
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
- for (std::map<Record*, std::set<Record*> >::iterator
+ for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
else
OS << Reg.getName();
OS << "\",\t\"";
- if (!Reg.TheDef->getValueAsString("Name").empty()) {
- OS << Reg.TheDef->getValueAsString("Name");
- } else {
- // Default to "name".
- if (!Reg.TheDef->getValueAsString("AsmName").empty())
- OS << Reg.TheDef->getValueAsString("AsmName");
- else
- OS << Reg.getName();
- }
- OS << "\",\t";
+ OS << Reg.getName() << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
OS << Reg.getName() << "_AliasSet,\t";
else
OS << "unsigned " << ClassName
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
<< " switch (RegNo) {\n"
- << " default: abort(); break;\n";
+ << " default:\n return 0;\n";
for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
OS << " case " << getQualifiedName(I->first) << ":\n";
OS << " switch (Index) {\n";
- OS << " default: abort(); break;\n";
+ OS << " default: return 0;\n";
for (unsigned i = 0, e = I->second.size(); i != e; ++i)
OS << " case " << (I->second)[i].first << ": return "
<< getQualifiedName((I->second)[i].second) << ";\n";
- OS << " }; break;\n";
+ OS << " };\n" << " break;\n";
}
OS << " };\n";
OS << " return 0;\n";
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
- << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
+ << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
+ << " SubregHashTable, SubregHashTableSize) {\n"
+ << "}\n\n";
// Collect all information about dwarf register numbers
unsigned maxLength = 0;
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
Record *Reg = Registers[i].TheDef;
- std::vector<int> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
+ std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
}
// Now we know maximal length of number list. Append -1's, where needed
- for (std::map<Record*, std::vector<int> >::iterator
- I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
+ for (DwarfRegNumsMapTy::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
<< " default:\n"
<< " assert(0 && \"Invalid RegNum\");\n"
<< " return -1;\n";
+
+ // Sort by name to get a stable order.
+
- for (std::map<Record*, std::vector<int> >::iterator
+ for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
if (RegNo != -2)
projects / oota-llvm.git / blobdiff